From 3313a78e36da73f05da7402699f04909595a0c9d Mon Sep 17 00:00:00 2001 From: zaolin Date: Wed, 31 Oct 2018 16:43:43 +0100 Subject: northbridge/intel/fsp_*: Remove legacy SoCs * Remove FSP Sandy/Ivybrige which are unused. * Open Source implementation isn't final but good enough to replace FSP version. * For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE and NORTHBRIDGE_INTEL_SANDYBRIDGE Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e Signed-off-by: Philipp Deppenwiese Reviewed-on: https://review.coreboot.org/29402 Reviewed-by: Nico Huber Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/fsp_i89xx/elog.c | 109 --------------------------------- 1 file changed, 109 deletions(-) delete mode 100644 src/southbridge/intel/fsp_i89xx/elog.c (limited to 'src/southbridge/intel/fsp_i89xx/elog.c') diff --git a/src/southbridge/intel/fsp_i89xx/elog.c b/src/southbridge/intel/fsp_i89xx/elog.c deleted file mode 100644 index 3299d4b9d1..0000000000 --- a/src/southbridge/intel/fsp_i89xx/elog.c +++ /dev/null @@ -1,109 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "pch.h" - -void pch_log_state(void) -{ - u16 pm1_sts, gen_pmcon_3, tco2_sts; - u32 gpe0_sts, gpe0_en; - u8 gen_pmcon_2; - int i; - struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); - if (!lpc) - return; - - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS); - gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN); - tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS); - gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2); - gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3); - - /* PWR_FLR Power Failure */ - if (gen_pmcon_2 & (1 << 0)) - elog_add_event(ELOG_TYPE_POWER_FAIL); - - /* SUS Well Power Failure */ - if (gen_pmcon_3 & (1 << 14)) - elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); - - /* SYS_PWROK Failure */ - if (gen_pmcon_2 & (1 << 1)) - elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL); - - /* PWROK Failure */ - if (gen_pmcon_2 & (1 << 0)) - elog_add_event(ELOG_TYPE_PWROK_FAIL); - - /* Second TCO Timeout */ - if (tco2_sts & (1 << 1)) - elog_add_event(ELOG_TYPE_TCO_RESET); - - /* Power Button Override */ - if (pm1_sts & (1 << 11)) - elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); - - /* System Reset Status (reset button pushed) */ - if (gen_pmcon_2 & (1 << 4)) - elog_add_event(ELOG_TYPE_RESET_BUTTON); - - /* General Reset Status */ - if (gen_pmcon_3 & (1 << 9)) - elog_add_event(ELOG_TYPE_SYSTEM_RESET); - - /* ACPI Wake */ - if (pm1_sts & (1 << 15)) - elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, - acpi_is_wakeup_s3() ? 3 : 5); - - /* - * Wake sources - */ - - /* RTC */ - if (pm1_sts & (1 << 10)) - elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - - /* PCI Express (TODO: determine wake device) */ - if (pm1_sts & (1 << 14)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); - - /* PME (TODO: determine wake device) */ - if (gpe0_sts & (1 << 13)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0); - - /* Internal PME (TODO: determine wake device) */ - if (gpe0_sts & (1 << 13)) - elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); - - /* GPIO 0-15 */ - for (i = 0; i < 16; i++) { - if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i)))) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); - } - - /* SMBUS Wake */ - if (gpe0_sts & (1 << 7)) - elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0); -} -- cgit v1.2.3