From 3313a78e36da73f05da7402699f04909595a0c9d Mon Sep 17 00:00:00 2001 From: zaolin Date: Wed, 31 Oct 2018 16:43:43 +0100 Subject: northbridge/intel/fsp_*: Remove legacy SoCs * Remove FSP Sandy/Ivybrige which are unused. * Open Source implementation isn't final but good enough to replace FSP version. * For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE and NORTHBRIDGE_INTEL_SANDYBRIDGE Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e Signed-off-by: Philipp Deppenwiese Reviewed-on: https://review.coreboot.org/29402 Reviewed-by: Nico Huber Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/fsp_i89xx/early_smbus.c | 58 --------------------------- 1 file changed, 58 deletions(-) delete mode 100644 src/southbridge/intel/fsp_i89xx/early_smbus.c (limited to 'src/southbridge/intel/fsp_i89xx/early_smbus.c') diff --git a/src/southbridge/intel/fsp_i89xx/early_smbus.c b/src/southbridge/intel/fsp_i89xx/early_smbus.c deleted file mode 100644 index 97d4381a55..0000000000 --- a/src/southbridge/intel/fsp_i89xx/early_smbus.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2012 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include "pch.h" - -void enable_smbus(void) -{ - pci_devfn_t dev; - - /* Set the SMBus device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x3); - - /* Check to make sure we've got the right device. */ - if (pci_read_config16(dev, 0x0) != 0x8086) { - die("SMBus controller not found!"); - } - - /* Set SMBus I/O base. */ - pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); - - /* Set SMBus enable. */ - pci_write_config8(dev, HOSTC, HST_EN); - - /* Set SMBus I/O space enable. */ - pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); - - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); - - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - printk(BIOS_DEBUG,"SMBus controller enabled.\n"); -} - -int smbus_read_byte(unsigned device, unsigned address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} -- cgit v1.2.3