From 5a4554a73f68247c4e00cb1a5d19fb504e9adb92 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Tue, 15 Sep 2015 12:44:37 -0600 Subject: southbridge/intel: Add FSP based i89xx southbridge support The Intel i89xx is a communications chipset that pairs with Sandy(Ivy)bridge processors. It has a lot in common with the bd82x6x chipset, but fewer devices and options. Change-Id: I11bcd1edc80f72a1b2521def9be0d1bde5789a79 Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/12166 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/southbridge/intel/fsp_i89xx/Kconfig | 58 +++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 src/southbridge/intel/fsp_i89xx/Kconfig (limited to 'src/southbridge/intel/fsp_i89xx/Kconfig') diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig new file mode 100644 index 0000000000..d1426d670b --- /dev/null +++ b/src/southbridge/intel/fsp_i89xx/Kconfig @@ -0,0 +1,58 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 Google Inc. +## Copyright (C) 2013 Sage Electronic Engineering, LLC. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc. +## + +config SOUTHBRIDGE_INTEL_FSP_I89XX + bool + +if SOUTHBRIDGE_INTEL_FSP_I89XX + +config SOUTH_BRIDGE_OPTIONS # dummy + def_bool y + select IOAPIC + select HAVE_HARD_RESET + select HAVE_SMI_HANDLER + select USE_WATCHDOG_ON_BOOT + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select SPI_FLASH + select COMMON_FADT + select HAVE_INTEL_FIRMWARE + +config EHCI_BAR + hex + default 0xfe700000 + + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/intel/fsp_i89xx/bootblock.c" + +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + +config HPET_MIN_TICKS + hex + default 0x80 + +endif -- cgit v1.2.3