From bde6d309dfafe58732ec46314a2d4c08974b62d4 Mon Sep 17 00:00:00 2001 From: Kevin Paul Herbert Date: Wed, 24 Dec 2014 18:43:20 -0800 Subject: x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert Signed-off-by: Alexandru Gagniuc Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins) --- src/southbridge/intel/fsp_bd82x6x/azalia.c | 21 +++++++++++---------- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 2 +- src/southbridge/intel/fsp_bd82x6x/early_init.c | 2 +- src/southbridge/intel/fsp_bd82x6x/me.c | 18 +++++++++--------- src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 18 +++++++++--------- src/southbridge/intel/fsp_bd82x6x/pch.h | 4 ++++ src/southbridge/intel/fsp_bd82x6x/sata.c | 10 +++++----- 7 files changed, 40 insertions(+), 35 deletions(-) (limited to 'src/southbridge/intel/fsp_bd82x6x') diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index 7a280c56e2..f4988d6ec3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -34,7 +34,7 @@ typedef struct southbridge_intel_bd82x6x_config config_t; -static int set_bits(u32 port, u32 mask, u32 val) +static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; int count; @@ -63,7 +63,7 @@ static int set_bits(u32 port, u32 mask, u32 val) return 0; } -static int codec_detect(u32 base) +static int codec_detect(u8 *base) { u8 reg8; @@ -72,7 +72,8 @@ static int codec_detect(u32 base) goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + 0x0, read16(base + 0x0)); + write16(base + 0x0, + read16(base + 0x0)); /* Read in Codec location (BAR + 0xe)[2..0]*/ reg8 = read8(base + 0xe); @@ -118,7 +119,7 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) * no response would imply that the codec is non-operative */ -static int wait_for_ready(u32 base) +static int wait_for_ready(u8 *base) { /* Use a 50 usec timeout - the Linux kernel uses the * same duration */ @@ -126,7 +127,7 @@ static int wait_for_ready(u32 base) int timeout = 50; while(timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -141,7 +142,7 @@ static int wait_for_ready(u32 base) * is non-operative */ -static int wait_for_valid(u32 base) +static int wait_for_valid(u8 *base) { u32 reg32; @@ -165,7 +166,7 @@ static int wait_for_valid(u32 base) return -1; } -static void codec_init(struct device *dev, u32 base, int addr) +static void codec_init(struct device *dev, u8 *base, int addr) { u32 reg32; const u32 *verb; @@ -213,7 +214,7 @@ static void codec_init(struct device *dev, u32 base, int addr) printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); } -static void codecs_init(struct device *dev, u32 base, u32 codec_mask) +static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; for (i = 3; i >= 0; i--) { @@ -234,7 +235,7 @@ static void codecs_init(struct device *dev, u32 base, u32 codec_mask) static void azalia_init(struct device *dev) { - u32 base; + u8 *base; struct resource *res; u32 codec_mask; u8 reg8; @@ -248,7 +249,7 @@ static void azalia_init(struct device *dev) // NOTE this will break as soon as the Azalia get's a bar above // 4G. Is there anything we can do about it? - base = (u32)res->base; + base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); if (RCBA32(0x2030) & (1 << 31)) { diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 9b3e97aa34..c42a79733a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -58,7 +58,7 @@ static void enable_port80_on_lpc(void) pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ - pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); + pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); u32 reg32 = *gcs; reg32 = reg32 & ~0x04; diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c index c89395dcf5..7b630f4143 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_init.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c @@ -143,7 +143,7 @@ static void sandybridge_setup_bars(void) { /* Setting up Southbridge. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 5326eb5402..bcaeeeb232 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -63,7 +63,7 @@ static const char *me_bios_path_values[] = { #endif /* MMIO base address for MEI interface */ -static u32 mei_base_address; +static u32 *mei_base_address; #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) static inline void mei_read_dword_ptr(void *ptr, int offset) { - u32 dword = read32(mei_base_address + offset); + u32 dword = read32(mei_base_address + (offset/sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } @@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); + write32(mei_base_address + (offset/sizeof(u32)), dword); mei_dump(ptr, dword, offset, "WRITE"); } @@ -144,13 +144,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + MEI_H_CB_WW, dword); + write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -500,11 +500,11 @@ static void intel_me7_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *) + (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) + if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ @@ -626,7 +626,7 @@ static int intel_mei_setup(device_t dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = res->base; + mei_base_address = res2mmio(res, 0, 0); /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index d673ac783c..9af5f9386c 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -64,7 +64,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); #endif /* MMIO base address for MEI interface */ -static u32 mei_base_address; +static u32 *mei_base_address; #if CONFIG_DEBUG_INTEL_ME static void mei_dump(void *ptr, int dword, int offset, const char *type) @@ -106,7 +106,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type) static inline void mei_read_dword_ptr(void *ptr, int offset) { - u32 dword = read32(mei_base_address + offset); + u32 dword = read32(mei_base_address + (offset/sizeof(u32))); memcpy(ptr, &dword, sizeof(dword)); mei_dump(ptr, dword, offset, "READ"); } @@ -115,7 +115,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset) { u32 dword = 0; memcpy(&dword, ptr, sizeof(dword)); - write32(mei_base_address + offset, dword); + write32(mei_base_address + (offset/sizeof(u32)), dword); mei_dump(ptr, dword, offset, "WRITE"); } @@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr) static inline void write_cb(u32 dword) { - write32(mei_base_address + MEI_H_CB_WW, dword); + write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword); mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE"); } static inline u32 read_cb(void) { - u32 dword = read32(mei_base_address + MEI_ME_CB_RW); + u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32))); mei_dump(NULL, dword, MEI_ME_CB_RW, "READ"); return dword; } @@ -494,11 +494,11 @@ void intel_me8_finalize_smm(void) struct me_hfs hfs; u32 reg32; - mei_base_address = - pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf; + mei_base_address = (u32 *) + (pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); /* S3 path will have hidden this device already */ - if (!mei_base_address || mei_base_address == 0xfffffff0) + if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; /* Make sure ME is in a mode that expects EOP */ @@ -613,7 +613,7 @@ static int intel_mei_setup(device_t dev) printk(BIOS_DEBUG, "ME: MEI resource not present!\n"); return -1; } - mei_base_address = res->base; + mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ reg32 = pci_read_config32(dev, PCI_COMMAND); diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index a06ca7421e..c1e9b71810 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -48,7 +48,11 @@ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0400 +#ifndef __ACPI__ +#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#else #define DEFAULT_RCBA 0xfed1c000 +#endif #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/fsp_bd82x6x/sata.c b/src/southbridge/intel/fsp_bd82x6x/sata.c index 591bdbc3d0..ff0e20bfd8 100644 --- a/src/southbridge/intel/fsp_bd82x6x/sata.c +++ b/src/southbridge/intel/fsp_bd82x6x/sata.c @@ -57,7 +57,7 @@ static void sata_init(struct device *dev) reg16 &= ~PCI_COMMAND_MEMORY; pci_write_config16(dev, PCI_COMMAND, reg16); } else if(config->sata_ahci) { - u32 abar; + u32 *abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -66,12 +66,12 @@ static void sata_init(struct device *dev) pci_write_config8(dev, INTR_LN, 0x0a); /* Initialize AHCI memory-mapped space */ - abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); - printk(BIOS_DEBUG, "ABAR: %08X\n", abar); + abar = (u32 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); + printk(BIOS_DEBUG, "ABAR: %p\n", abar); /* Enable AHCI Mode */ - reg32 = read32(abar + 0x04); + reg32 = read32(abar + 0x01); reg32 |= (1 << 31); - write32(abar + 0x04, reg32); + write32(abar + 0x01, reg32); } else { printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); -- cgit v1.2.3