From b85a87b7d6f9f12d5c71c32741c8af731ed6be7e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 29 Dec 2014 11:32:27 +0200 Subject: intel SMI handlers: Refactor GPI SMI/SCI routing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the GPI interrupt routing selection between SMI/SCI from mainboards to southbridge. There is speculation if this is all just legacy APM stuff that could be removed with a followup. Change-Id: Iab14cf347584513793f417febc47f0559e17f5a5 Signed-off-by: Kyösti Mälkki Signed-off-by: Nicolas Reinecke Reviewed-on: http://review.coreboot.org/7967 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens --- src/southbridge/intel/fsp_bd82x6x/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel/fsp_bd82x6x') diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index f9961f95ba..6b95d0874a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -185,7 +185,7 @@ static void pch_gpi_routing(device_t dev) reg32 |= (config->gpi14_routing & 0x03) << 28; reg32 |= (config->gpi15_routing & 0x03) << 30; - pci_write_config32(dev, 0xb8, reg32); + pci_write_config32(dev, GPIO_ROUT, reg32); } static void pch_power_options(device_t dev) -- cgit v1.2.3