From 73a9b503f00675753f97227d967bb0adddb3ca00 Mon Sep 17 00:00:00 2001
From: Marc Jones <marc.jones@se-eng.com>
Date: Tue, 29 Oct 2013 22:12:32 -0600
Subject: Add Intel FSP bd82x6x southbridge support

Add support for the bd82x6x using the Intel FSP.
The FSP is different enough to warrant its own source files
for now. The mrc/system agent chromebook solution does much more
southbridge initialization and configuration than the FSP version.
It may be combined in the future.

Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 71 ++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)
 create mode 100644 src/southbridge/intel/fsp_bd82x6x/Makefile.inc

(limited to 'src/southbridge/intel/fsp_bd82x6x/Makefile.inc')

diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
new file mode 100644
index 0000000000..dac12411ff
--- /dev/null
+++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc
@@ -0,0 +1,71 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+## Copyright (C) 2013 Sage Electronic Engineering, LLC.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+ifeq ($(CONFIG_INCLUDE_ME),y)
+INTERMEDIATE+=bd82x6x_add_me
+endif
+
+ramstage-y += pch.c
+ramstage-y += azalia.c
+ramstage-y += lpc.c
+ramstage-y += sata.c
+ramstage-y += me.c
+ramstage-y += me_8.x.c
+ramstage-y += me_status.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
+
+ramstage-$(CONFIG_ELOG) += elog.c
+ramstage-y += spi.c
+smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
+
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c
+
+romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c early_init.c
+romstage-$(CONFIG_USBDEBUG) += usb_debug.c
+ramstage-$(CONFIG_USBDEBUG) += usb_debug.c
+smm-$(CONFIG_USBDEBUG) += usb_debug.c
+romstage-y += reset.c
+romstage-y += early_spi.c
+
+bd82x6x_add_me: $(obj)/coreboot.pre $(IFDTOOL)
+	printf "    DD         Adding Intel Firmware Descriptor\n"
+	dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \
+		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
+	printf "    IFDTOOL    me.bin -> coreboot.pre\n"
+	$(objutil)/ifdtool/ifdtool \
+		-i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/me.bin \
+		$(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
+	printf "    IFDTOOL    Locking Management Engine\n"
+	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+else
+	printf "    IFDTOOL    Unlocking Management Engine\n"
+	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
+	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
+endif
+
+PHONY += bd82x6x_add_me
-- 
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