From 2dd3f877cc7926f5ac1cfd5a7e5d546c8be2121c Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 25 Apr 2014 15:09:27 -0600 Subject: cougar_canyon2: Switch CPU/NB/SB to the shared FSP code CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/southbridge/intel/fsp_bd82x6x/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/southbridge/intel/fsp_bd82x6x/Makefile.inc') diff --git a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc index 7088caa59a..a1d3e62e7c 100644 --- a/src/southbridge/intel/fsp_bd82x6x/Makefile.inc +++ b/src/southbridge/intel/fsp_bd82x6x/Makefile.inc @@ -69,3 +69,5 @@ else endif PHONY += bd82x6x_add_me + +INCLUDES += -I$(src)/southbridge/intel/fsp_bd82x6x -- cgit v1.2.3