From 54c586c7e76d9e9ec75ccebaf1555b3fde6114e8 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 10 Jun 2013 11:40:54 +0300 Subject: usbdebug: Unify Intel southbridge builds MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit EHCI controller enable is identical on the affected chipsets. Change-Id: I91830b6f5144a70b158ec1ee40e9cba5fab3fbc9 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3424 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Marc Jones --- src/southbridge/intel/common/Makefile.inc | 22 ++++++++++++++ src/southbridge/intel/common/usb_debug.c | 50 +++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 src/southbridge/intel/common/Makefile.inc create mode 100644 src/southbridge/intel/common/usb_debug.c (limited to 'src/southbridge/intel/common') diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc new file mode 100644 index 0000000000..06fa416242 --- /dev/null +++ b/src/southbridge/intel/common/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2008-2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_USBDEBUG) += usb_debug.c +ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +smm-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c new file mode 100644 index 0000000000..397c6864d5 --- /dev/null +++ b/src/southbridge/intel/common/usb_debug.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif +#include +#include +#include +#include +#include + +/* Required for successful build, but currently empty. */ +void set_debug_port(unsigned int port) +{ + /* Not needed, the ICH* southbridges hardcode physical USB port 1. */ +} + +void enable_usbdebug(unsigned int port) +{ + u32 dbgctl; + device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ + + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Force ownership of the Debug Port to the EHCI controller. */ + dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); + dbgctl |= (1 << 30); + write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); +} -- cgit v1.2.3