From 853bb4dc11f999d3f5637769da588fbd9446aba8 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <patrick.rudolph@9elements.com>
Date: Thu, 28 Jun 2018 13:58:36 +0200
Subject: sb/intel/common: Add functions to manipulate PMBASE

Add common functions to manipulate PMBASE IO window.

TODO:
* Use the new functions to manipulate register in PMBASE.
* Get rid of duplicated get_pmbase()

Change-Id: I3b454434ade560fb056b1fc0afe9541df93e14dd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/27278
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/common/pmbase.c | 93 +++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100644 src/southbridge/intel/common/pmbase.c

(limited to 'src/southbridge/intel/common/pmbase.c')

diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c
new file mode 100644
index 0000000000..360b63d9e4
--- /dev/null
+++ b/src/southbridge/intel/common/pmbase.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Patrick Rudolph <patrick.rudolph@9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/early_variables.h>
+#include <assert.h>
+
+#include "pmbase.h"
+
+/* LPC PM Base Address Register */
+#define PMBASE		0x40
+#define PMSIZE		0x80
+
+/* PCI Configuration Space (D31:F0): LPC */
+#if defined(__SIMPLE_DEVICE__)
+#define PCH_LPC_DEV	PCI_DEV(0, 0x1f, 0)
+#else
+#define PCH_LPC_DEV	dev_find_slot(0, PCI_DEVFN(0x1f, 0))
+#endif
+
+u16 lpc_get_pmbase(void)
+{
+#if defined(__SMM__)
+	/* Don't assume PMBASE is still the same */
+	return pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
+#else
+	static u16 pmbase CAR_GLOBAL;
+
+	if (pmbase)
+		return pmbase;
+
+	pmbase = pci_read_config16(PCH_LPC_DEV, PMBASE) & 0xfffc;
+
+	return pmbase;
+#endif
+}
+
+void write_pmbase32(const u8 addr, const u32 val)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u32)));
+
+	outl(val, lpc_get_pmbase() + addr);
+}
+
+void write_pmbase16(const u8 addr, const u16 val)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u16)));
+
+	outw(val, lpc_get_pmbase() + addr);
+}
+
+void write_pmbase8(const u8 addr, const u8 val)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u8)));
+
+	outb(val, lpc_get_pmbase() + addr);
+}
+
+u32 read_pmbase32(const u8 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u32)));
+
+	return inl(lpc_get_pmbase() + addr);
+}
+
+u16 read_pmbase16(const u8 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u16)));
+
+	return inw(lpc_get_pmbase() + addr);
+}
+
+u8 read_pmbase8(const u8 addr)
+{
+	ASSERT(addr <= (PMSIZE - sizeof(u8)));
+
+	return inb(lpc_get_pmbase() + addr);
+}
-- 
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