From d6eb72c87eb569000df62456c187329ee4967dc1 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 12 Jan 2021 15:09:57 +0100 Subject: build system: Structure and serialize INTERMEDIATE Target added to INTERMEDIATE all operate on coreboot.pre, each modifying the file in some way. When running them in parallel, coreboot.pre can be read from and written to in parallel which can corrupt the result. Add a function to create those rules that also adds existing INTERMEDIATE targets to enforce an order (as established by evaluation order of Makefile.inc files). While at it, also add the addition to the PHONY target so we don't forget it. BUG=chromium:1154313, b:174585424 TEST=Built a configuration with SeaBIOS + SeaBIOS config files (ps2 timeout and sercon) and saw that they were executed. Change-Id: Ia5803806e6c33083dfe5dec8904a65c46436e756 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/49358 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/southbridge/intel/common/firmware/Makefile.inc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/southbridge/intel/common/firmware') diff --git a/src/southbridge/intel/common/firmware/Makefile.inc b/src/southbridge/intel/common/firmware/Makefile.inc index a542d7eff1..127da190b4 100644 --- a/src/southbridge/intel/common/firmware/Makefile.inc +++ b/src/southbridge/intel/common/firmware/Makefile.inc @@ -7,8 +7,7 @@ ifeq ($(CONFIG_HAVE_INTEL_FIRMWARE),y) # image outside of CBFS ifeq ($(CONFIG_HAVE_IFD_BIN),y) -PHONY+=add_intel_firmware -INTERMEDIATE+=add_intel_firmware +$(call add_intermediate, add_intel_firmware) else ifeq ($(CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED),y) files_added:: warn_intel_firmware endif @@ -107,6 +106,6 @@ warn_intel_firmware: printf "board's flash chip! You can use flashrom's IFD or layout\n" printf "parameters to flash only to the BIOS region.\n\n" -PHONY+=add_intel_firmware warn_intel_firmware +PHONY+=warn_intel_firmware endif -- cgit v1.2.3