From 45022ae056cdbf58429b77daf2da176306312801 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 1 Oct 2018 19:17:11 +0200 Subject: intel: Use CF9 reset (part 1) Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/southbridge/intel/common/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/southbridge/intel/common/Makefile.inc') diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 961b71bbd8..249d2496ef 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -16,6 +16,12 @@ # CONFIG_HAVE_INTEL_FIRMWARE protects doing anything to the build. subdirs-y += firmware +verstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c +postcar-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET) += reset.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-y += pmbase.c -- cgit v1.2.3