From 47a6603f34481e1226c106002c9fd7fb3d0c2c04 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 25 Oct 2019 23:43:14 +0200 Subject: sb/intel/common/spi: Add Baytrail/Braswell support The mechanism for getting the SPIBAR is little different. Tested on Intel Minnowboard Turbot. Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/common/Kconfig | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/southbridge/intel/common/Kconfig') diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 18bcd2e4a6..d1b6bf6024 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -24,6 +24,18 @@ config SOUTHBRIDGE_INTEL_COMMON_SPI select SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES +config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + +config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + +config SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT + def_bool n + select SOUTHBRIDGE_INTEL_COMMON_SPI + config SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN def_bool n -- cgit v1.2.3