From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/southbridge/intel/bd82x6x/elog.c | 2 +- src/southbridge/intel/bd82x6x/lpc.c | 4 ++-- src/southbridge/intel/bd82x6x/pch.c | 12 ++++-------- src/southbridge/intel/bd82x6x/watchdog.c | 2 +- 4 files changed, 8 insertions(+), 12 deletions(-) (limited to 'src/southbridge/intel/bd82x6x') diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index 2ccdf83c4d..ef345efb75 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -30,7 +30,7 @@ void pch_log_state(void) u32 gpe0_sts, gpe0_en; u8 gen_pmcon_2; int i; - struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *lpc = pcidev_on_root(0x1f, 0); if (!lpc) return; diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7ae538ebd2..d3da239321 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -738,7 +738,7 @@ static void southbridge_inject_dsdt(struct device *dev) void acpi_fill_fadt(acpi_fadt_t *fadt) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; int c2_latency; @@ -875,7 +875,7 @@ static const char *lpc_acpi_name(const struct device *dev) static void southbridge_fill_ssdt(struct device *device) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 00265d0219..1a646b17b9 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -32,11 +32,9 @@ int pch_silicon_revision(void) static int pch_revision_id = -1; #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); #endif if (pch_revision_id < 0) @@ -49,11 +47,9 @@ int pch_silicon_type(void) static int pch_type = -1; #ifdef __SIMPLE_DEVICE__ - pci_devfn_t dev; - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); #else - struct device *dev; - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = pcidev_on_root(0x1f, 0); #endif if (pch_type < 0) diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c index eb4d38cd2c..c186f353ba 100644 --- a/src/southbridge/intel/bd82x6x/watchdog.c +++ b/src/southbridge/intel/bd82x6x/watchdog.c @@ -34,7 +34,7 @@ void watchdog_off(void) struct device *dev; /* Get LPC device. */ - dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + dev = pcidev_on_root(0x1f, 0); /* Disable interrupt. */ value = pci_read_config16(dev, PCI_COMMAND); -- cgit v1.2.3