From 89739baf531e26dc81420df4f943bf8c163a0c0d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 25 Jul 2020 02:46:39 +0200 Subject: {sb,soc}/intel/**/*.c: Use macros for PCI COMMAND bits We have definitions for the bits in the PCI COMMAND register. Use them. Also add spaces around bitwise operators, to comply with the code style. Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/southbridge/intel/bd82x6x/lpc.c | 4 +++- src/southbridge/intel/bd82x6x/sata.c | 3 ++- 2 files changed, 5 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/bd82x6x') diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 2efddd89a1..2407d92dc1 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -520,7 +520,9 @@ static void lpc_init(struct device *dev) report_pch_info(dev); /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, 0x000f); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* IO APIC initialization. */ pch_enable_ioapic(dev); diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 63801a213e..484f0f11a2 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -108,7 +108,8 @@ static void sata_init(struct device *dev) /* SATA configuration */ /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, 0x0007); + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); /* AHCI */ if (sata_mode == 0) { -- cgit v1.2.3