From 307320c23f2c1907ff6cf6fa87608d1155aba05f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 21 Nov 2022 17:27:07 +0200 Subject: sb,soc/intel: Address TCO SECOND_TO_STS name collision MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Angel Pons Reviewed-by: Subrata Banik --- src/southbridge/intel/bd82x6x/pch.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel/bd82x6x') diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index b5e05f6578..3aef48a56b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -469,7 +469,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define TCO1_TIMEOUT (1 << 3) #define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 -#define SECOND_TO_STS (1 << 1) +#define TCO2_STS_SECOND_TO (1 << 1) #define TCO1_CNT 0x68 #define TCO_TMR_HLT (1 << 11) #define TCO_LOCK (1 << 12) -- cgit v1.2.3