From 12b121cdb450d96309dd96b2ccc25fc5501d2250 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sun, 18 Aug 2019 16:33:39 +0300
Subject: southbridge/intel: Tidy up preprocessor and headers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/intel/bd82x6x/azalia.c   |  2 ++
 src/southbridge/intel/bd82x6x/lpc.c      |  1 +
 src/southbridge/intel/bd82x6x/me.h       |  5 +----
 src/southbridge/intel/bd82x6x/pch.c      |  4 +++-
 src/southbridge/intel/bd82x6x/pch.h      | 20 ++++++++------------
 src/southbridge/intel/bd82x6x/pcie.c     |  2 ++
 src/southbridge/intel/bd82x6x/sata.c     |  1 +
 src/southbridge/intel/bd82x6x/usb_xhci.c |  1 +
 8 files changed, 19 insertions(+), 17 deletions(-)

(limited to 'src/southbridge/intel/bd82x6x')

diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index e3379d6af0..744fe7d6a6 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -23,6 +23,8 @@
 #include <device/mmio.h>
 #include <delay.h>
 #include <device/azalia_device.h>
+
+#include "chip.h"
 #include "pch.h"
 
 #define HDA_ICII_REG 0x68
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index bd3c993912..592c70f8b4 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -32,6 +32,7 @@
 #include <cpu/x86/smm.h>
 #include <cbmem.h>
 #include <string.h>
+#include "chip.h"
 #include "pch.h"
 #include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 270886485d..203d0c038b 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -238,17 +238,14 @@ typedef enum {
 /* Defined in me_status.c for both romstage and ramstage */
 void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
 
-#ifdef __PRE_RAM__
 void intel_early_me_status(void);
 int intel_early_me_init(void);
 int intel_early_me_uma_size(void);
 int intel_early_me_init_done(u8 status);
-#endif
 
-#ifdef __SMM__
 void intel_me_finalize_smm(void);
 void intel_me8_finalize_smm(void);
-#endif
+
 typedef struct {
 	u32       major_version  : 16;
 	u32       minor_version  : 16;
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index e4eccd766d..475def33e4 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -24,9 +24,11 @@
 #include <device/pci.h>
 #endif
 #include <device/pci_ops.h>
-#include "pch.h"
 #include <string.h>
 
+#include "chip.h"
+#include "pch.h"
+
 int pch_silicon_revision(void)
 {
 	static int pch_revision_id = -1;
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index bc6c8b333f..fcb15ac99e 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -56,20 +56,19 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
-#if !defined(__ASSEMBLER__)
-#if !defined(__PRE_RAM__)
-#if !defined(__SIMPLE_DEVICE__)
-#include "chip.h"
-void pch_enable(struct device *dev);
-#endif
+
 int pch_silicon_revision(void);
 int pch_silicon_type(void);
 int pch_silicon_supported(int type, int rev);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
-#else /* __PRE_RAM__ */
+
 void enable_smbus(void);
 void enable_usb_bar(void);
+
+#if ENV_ROMSTAGE
 int smbus_read_byte(unsigned device, unsigned address);
+#endif
+
 void early_thermal_init(void);
 void southbridge_configure_default_intmap(void);
 void southbridge_rcba_config(void);
@@ -87,14 +86,11 @@ struct southbridge_usb_port
 };
 
 #ifndef __ROMCC__
+void pch_enable(struct device *dev);
 extern const struct southbridge_usb_port mainboard_usb_ports[14];
 #endif
 
-void
-early_usb_init (const struct southbridge_usb_port *portmap);
-
-#endif
-#endif
+void early_usb_init(const struct southbridge_usb_port *portmap);
 
 /* PM I/O Space */
 #define UPRWC			0x3c
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 97306e44cb..686930d80a 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -22,6 +22,8 @@
 #include <device/pci_ids.h>
 #include <southbridge/intel/common/pciehp.h>
 #include <assert.h>
+
+#include "chip.h"
 #include "pch.h"
 
 static void pch_pcie_pm_early(struct device *dev)
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 6a39873e7b..3ec065f287 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -24,6 +24,7 @@
 #include <acpi/sata.h>
 #include <types.h>
 
+#include "chip.h"
 #include "pch.h"
 
 typedef struct southbridge_intel_bd82x6x_config config_t;
diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c
index 85e450db5b..55c8948063 100644
--- a/src/southbridge/intel/bd82x6x/usb_xhci.c
+++ b/src/southbridge/intel/bd82x6x/usb_xhci.c
@@ -21,6 +21,7 @@
 #include "pch.h"
 #include <device/pci_ehci.h>
 #include <device/pci_ops.h>
+#include "chip.h"
 
 static void usb_xhci_init(struct device *dev)
 {
-- 
cgit v1.2.3