From 0edc22490a643c4b4c6181c42eed375485f9e0e4 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Mon, 29 Apr 2013 15:04:30 -0700 Subject: smi: Update mainboard_smi_gpi() to have 32bit argument With the LynxPoint chipset there are more than 16 possible GPIOs that can trigger an SMI so we need a mainboard handler that can support this. There are only a handful of users of this function so just change them all to use the new prototype. Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/49530 Reviewed-by: Stefan Reinauer Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4145 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/southbridge/intel/bd82x6x/smihandler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/intel/bd82x6x') diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 491f997ea5..99f6b51319 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -626,7 +626,7 @@ static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save) { - void (*mainboard_gpi)(u16 gpi_sts) = mainboard_smi_gpi; + void (*mainboard_gpi)(u32 gpi_sts) = mainboard_smi_gpi; u16 reg16; reg16 = inw(pmbase + ALT_GP_SMI_STS); outw(reg16, pmbase + ALT_GP_SMI_STS); @@ -638,7 +638,7 @@ static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_ mainboard_gpi(reg16); } else { if (reg16) - printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16); + printk(BIOS_DEBUG, "GPI (mask %04x)\n", reg16); } outw(reg16, pmbase + ALT_GP_SMI_STS); -- cgit v1.2.3