From 0b3512b495528adfe29fe7d9267a59361a6f01cd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 10 Aug 2020 13:02:20 +0200 Subject: sb/intel: Remove inexistent references to IDE controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This device doesn't exist on these southbridges. Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/44327 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner Reviewed-by: Arthur Heymans --- src/southbridge/intel/bd82x6x/pch.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/southbridge/intel/bd82x6x') diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index b7842c085f..75529065f8 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -155,8 +155,7 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -- cgit v1.2.3