From c803f65206188ca74526054c54bce4f405a55850 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 7 Jun 2020 22:09:01 +0200 Subject: sb/intel/bd82x6x: Use PCI bitwise ops Some cases could not be factored out while keeping reproducibility. Also mark some potential bugs with a FIXME comment, since fixing them while also keeping the binary unchanged is pretty much impossible. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/southbridge/intel/bd82x6x/usb_xhci.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/usb_xhci.c') diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 5a5b418b43..8bd0641d9f 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -20,9 +20,7 @@ static void usb_xhci_init(struct device *dev) pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping); /* lock overcurrent map */ - reg32 = pci_read_config32(dev, 0x44); - reg32 |= 1; - pci_write_config32(dev, 0x44, reg32); + pci_or_config32(dev, 0x44, 1); pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports); pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports); -- cgit v1.2.3