From 729c0695e5e93d7f7e48ddd72787769ff62cd8b9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 19:50:44 +0200 Subject: sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40807 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/usb_ehci.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/usb_ehci.c') diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 0f3a1b9ca3..8bc45f69da 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -30,10 +30,8 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, 0xfc, 0x205b1708); #endif - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + //pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* For others, done in MRC. */ #if CONFIG(USE_NATIVE_RAMINIT) -- cgit v1.2.3