From b4a45dcf9d442b311dec7396a55be917713a0d15 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 26 Jul 2013 08:53:59 +0300
Subject: intel PCI ops: Remove explicit PCI MMCONF access
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MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17545
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/southbridge/intel/bd82x6x/smihandler.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/southbridge/intel/bd82x6x/smihandler.c')

diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 71ebb6e0e6..4cef988ef1 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -28,7 +28,7 @@
 #include "nvs.h"
 
 #include <northbridge/intel/sandybridge/sandybridge.h>
-#include <arch/pci_mmio_cfg.h>
+#include <arch/io.h>
 #include <southbridge/intel/bd82x6x/me.h>
 #include <southbridge/intel/common/gpio.h>
 #include <cpu/intel/model_206ax/model_206ax.h>
-- 
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