From 4f8b108288bf080762d28e5260ecf1d0a6e89697 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 14 Jul 2019 11:54:58 +0200 Subject: sb/intel/bd82x6x: Add and use more RCBA defines Taken from "Intel 6 Series Chipset and Intel C200 Series Chipset" Document Number: 324645-006 and "Intel 5 Series Chipset and Intel 3400 Series Chipset" Document Number: 322169-004 and "Intel 6 Series Chipset" Document Number: 324645-001. UPDCR was found in GNU/Linux's drivers/pci/quirks.c. DMC2 was guessed as it's close to DMC and defined for 5 series chipset. Test: Run BUILD_TIMELESS=1 and compared the coreboot.roms, no differences. Change-Id: I4fed7c38078cabd4308424c7547416e87c9e6fa7 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/34334 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/pcie.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel/bd82x6x/pcie.c') diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 0bc75b54a5..97306e44cb 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -114,7 +114,7 @@ static void pch_pcie_pm_early(struct device *dev) /* Adjust ASPM L1 exit latency */ reg32 = pci_read_config32(dev, 0x4c); reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15)); - if (RCBA32(0x2320) & (1 << 16)) { + if (RCBA32(CIR9) & (1 << 16)) { /* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */ reg32 |= (1 << 17); } else { -- cgit v1.2.3