From ece06dc2d1b6838c2c24daa6375586908144bef6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 5 May 2023 09:27:42 +0300 Subject: sb/intel/bd82x6x,ibexpeak: Move UPRWC definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Locate it with all the other PM IO registers. Change-Id: I779b2e313c9d8370c66c4adb4f6f4d4cf5b4e7dd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/74980 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/pch.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/pch.h') diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 8155479ebf..8face0649e 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -64,10 +64,6 @@ extern const struct southbridge_usb_port mainboard_usb_ports[14]; void early_usb_init(const struct southbridge_usb_port *portmap); -/* PM I/O Space */ -#define UPRWC 0x3c -#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ - /* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06 #define SMLT 0x1b @@ -459,6 +455,11 @@ void early_usb_init(const struct southbridge_usb_port *portmap); #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a + +/* PM I/O Space */ +#define UPRWC 0x3c +#define UPRWC_WR_EN (1 << 1) /* USB Per-Port Registers Write Enable */ + #define GPE_CNTL 0x42 #define DEVACT_STS 0x44 #define PM2_CNT 0x50 // mobile only -- cgit v1.2.3