From 7b2f9f6994341a890a11220a9d9fcbf7997bcae9 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Thu, 1 Oct 2015 19:00:51 +0200 Subject: intel/southbridge/bd82x6x: Add option to set SPI VSCC registers These are needed for the hardware-sequencing function of the PCH SPI interface. Values are specific to the flash chip used on a board. Change-Id: Id06766b4bac2686406bc09b8afa02f311f40dee7 Signed-off-by: Nico Huber Reviewed-on: http://review.coreboot.org/11798 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nicolas Reinecke Reviewed-by: Duncan Laurie --- src/southbridge/intel/bd82x6x/lpc.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/southbridge/intel/bd82x6x/lpc.c') diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 6bf43decef..a9e3ec56b5 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -480,6 +480,21 @@ static void pch_decode_init(struct device *dev) pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec); } +static void pch_spi_init(const struct device *const dev) +{ + const config_t *const config = dev->chip_info; + + printk(BIOS_DEBUG, "pch_spi_init\n"); + + if (config->spi_uvscc) + RCBA32(0x3800 + 0xc8) = config->spi_uvscc; + if (config->spi_lvscc) + RCBA32(0x3800 + 0xc4) = config->spi_lvscc; + + if (config->spi_uvscc || config->spi_lvscc) + RCBA32_OR(0x3800 + 0xc4, 1 << 23); /* lock both UVSCC + LVSCC */ +} + static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "pch: lpc_init\n"); @@ -536,6 +551,8 @@ static void lpc_init(struct device *dev) pch_set_acpi_mode(); pch_fixups(dev); + + pch_spi_init(dev); } static void pch_lpc_read_resources(device_t dev) -- cgit v1.2.3