From e7ae96f48834d57fd1a6c8940fa3f64b97520ed9 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Tue, 13 Nov 2012 15:07:45 -0700 Subject: Add Intel Panther Point USB3 initialization Add PEI updates and ACPI updates for supporting EHCI to XHCI USB port support. Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/2519 Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/southbridge/intel/bd82x6x/early_usb.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/southbridge/intel/bd82x6x/early_usb.c') diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index b2e009123e..bbe792f908 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -27,6 +27,7 @@ #define PCH_EHCI1_TEMP_BAR0 0xe8000000 #define PCH_EHCI2_TEMP_BAR0 0xe8000400 +#define PCH_XHCI_TEMP_BAR0 0xe8001000 /* * Setup USB controller MMIO BAR to prevent the @@ -39,6 +40,7 @@ void enable_usb_bar(void) { device_t usb0 = PCH_EHCI1_DEV; device_t usb1 = PCH_EHCI2_DEV; + device_t usb3 = PCH_XHCI_DEV; u32 cmd; /* USB Controller 1 */ @@ -54,4 +56,11 @@ void enable_usb_bar(void) cmd = pci_read_config32(usb1, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config32(usb1, PCI_COMMAND, cmd); + + /* USB3 Controller */ + pci_write_config32(usb3, PCI_BASE_ADDRESS_0, + PCH_XHCI_TEMP_BAR0); + cmd = pci_read_config32(usb3, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(usb3, PCI_COMMAND, cmd); } -- cgit v1.2.3