From 4513020064cc4765e723f6f3cc2b8a45a0dc6545 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Fri, 4 Jan 2019 14:23:54 +0100
Subject: cpu/intel: Use the common code to initialize the romstage timestamps
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The initial timestamps are now pushed on the stack when entering the
romstage C code.

Tested on Asus P5QC.

Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
---
 src/southbridge/intel/bd82x6x/early_pch_common.c | 11 -----------
 1 file changed, 11 deletions(-)

(limited to 'src/southbridge/intel/bd82x6x/early_pch_common.c')

diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c
index 3e151fcb75..a9ec9b1a2c 100644
--- a/src/southbridge/intel/bd82x6x/early_pch_common.c
+++ b/src/southbridge/intel/bd82x6x/early_pch_common.c
@@ -15,8 +15,6 @@
  */
 
 #include <arch/io.h>
-#include <timestamp.h>
-#include <cpu/x86/tsc.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
 #include "pch.h"
@@ -25,15 +23,6 @@
 #include <rules.h>
 
 #if ENV_ROMSTAGE
-uint64_t get_initial_timestamp(void)
-{
-	tsc_t base_time = {
-		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
-		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
-	};
-	return tsc_to_uint64(base_time);
-}
-
 int southbridge_detect_s3_resume(void)
 {
 	u32 pm1_cnt;
-- 
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