From e2f0a5f76c8a525396f627b8ba97e8913ab14fc6 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 24 Mar 2019 14:47:47 +0100 Subject: sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Tested on Lenovo T520 (Intel Sandy Bridge) with Change I8afc9f966033f45823f5dfde279e0f66de165e93 applied as well. Still boots to OS, no errors visible in dmesg and S3 resume is working. Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/32037 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/southbridge/intel/bd82x6x/Makefile.inc | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/southbridge/intel/bd82x6x/Makefile.inc') diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 24d7e2d24e..7ce3da70ad 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,7 +38,7 @@ ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += early_spi.c early_pch_common.c +romstage-y += early_spi.c romstage-y += early_rcba.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -47,6 +47,4 @@ else romstage-y += early_me_mrc.c early_usb_mrc.c endif -ramstage-y += early_pch_common.c - endif -- cgit v1.2.3