From 47a6603f34481e1226c106002c9fd7fb3d0c2c04 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 25 Oct 2019 23:43:14 +0200 Subject: sb/intel/common/spi: Add Baytrail/Braswell support The mechanism for getting the SPIBAR is little different. Tested on Intel Minnowboard Turbot. Change-Id: Ib14f185eab8bf708ad82b06c7a7ce586744318fd Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36342 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/southbridge/intel/bd82x6x/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/intel/bd82x6x/Kconfig') diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 1c7e9b7da6..8b8f6b361a 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -27,7 +27,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON_FINALIZE select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS - select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select SOUTHBRIDGE_INTEL_COMMON_PMBASE select SOUTHBRIDGE_INTEL_COMMON_RTC -- cgit v1.2.3