From 9fe4d797a37671a65053add3f7cca27397db0b9b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 16 Jan 2010 17:53:38 +0000 Subject: coreboot used to have two different "APIs" for memory accesses: read32(unsigned long addr) vs readl(void *addr) and write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr) read32 was only available in __PRE_RAM__ stage, while readl was used in stage2. Some unclean implementations then made readl available to __PRE_RAM__ too which results in really messy includes and code. This patch fixes all code to use the read32/write32 variant, so that we can remove readl/writel in another patch. Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/broadcom/bcm5785/bcm5785_sata.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'src/southbridge/broadcom') diff --git a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c index 38cd6d4b3d..6818e6a2b0 100644 --- a/src/southbridge/broadcom/bcm5785/bcm5785_sata.c +++ b/src/southbridge/broadcom/bcm5785/bcm5785_sata.c @@ -52,13 +52,13 @@ static void sata_init(struct device *dev) printk_debug("init PHY...\n"); for(i=0; i<4; i++) { mmio = base + 0x100 * i; - byte = readb(mmio + 0x40); + byte = read8(mmio + 0x40); printk_debug("port %d PHY status = %02x\r\n", i, byte); if(byte & 0x4) {// bit 2 is set - byte = readb(mmio+0x48); - writeb(byte | 1, mmio + 0x48); - writeb(byte & (~1), mmio + 0x48); - byte = readb(mmio + 0x40); + byte = read8(mmio+0x48); + write8(mmio + 0x48, byte | 1); + write8(mmio + 0x48, byte & (~1)); + byte = read8(mmio + 0x40); printk_debug("after reset port %d PHY status = %02x\r\n", i, byte); } } -- cgit v1.2.3