From f1b58b78351d7ed220673e688a2f7bc9e96da4e2 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Fri, 1 Mar 2019 13:43:02 +0200
Subject: device/pci: Fix PCI accessor headers
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PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.

Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/southbridge/broadcom/bcm5785/bcm5785.c     | 1 +
 src/southbridge/broadcom/bcm5785/bootblock.c   | 1 +
 src/southbridge/broadcom/bcm5785/early_smbus.c | 1 +
 3 files changed, 3 insertions(+)

(limited to 'src/southbridge/broadcom/bcm5785')

diff --git a/src/southbridge/broadcom/bcm5785/bcm5785.c b/src/southbridge/broadcom/bcm5785/bcm5785.c
index 53ee8d4698..beaa94aeef 100644
--- a/src/southbridge/broadcom/bcm5785/bcm5785.c
+++ b/src/southbridge/broadcom/bcm5785/bcm5785.c
@@ -16,6 +16,7 @@
 
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include "bcm5785.h"
 
diff --git a/src/southbridge/broadcom/bcm5785/bootblock.c b/src/southbridge/broadcom/bcm5785/bootblock.c
index 62b20a3f7b..3f7443694d 100644
--- a/src/southbridge/broadcom/bcm5785/bootblock.c
+++ b/src/southbridge/broadcom/bcm5785/bootblock.c
@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/pci_type.h>
 
diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
index c702c651ba..260f1fc01a 100644
--- a/src/southbridge/broadcom/bcm5785/early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/early_smbus.c
@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include "smbus.h"
 
 #define SMBUS_IO_BASE 0x1000
-- 
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