From f69c96dd8d857a90143f1c2f38efd19e26b68039 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Thu, 13 Jun 2019 14:33:20 -0600 Subject: sb/amd/sr5650: Use 32 bit integers when disabling ports This function attempts to set bits in the 20s of state and state_save, which won't work since those variables are only 16 bits wide. Extend them to 32 bits to capture all the bit operations. Change-Id: I5616a2d879a85ff5f57af5af20384516659c62d6 Signed-off-by: Jacob Garber Found-by: Coverity CID 1347384 Reviewed-on: https://review.coreboot.org/c/coreboot/+/33457 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/amd/sr5650/pcie.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/amd') diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index f87fadbb08..6c42fdde4d 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -59,11 +59,11 @@ static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 { printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port); u32 reg; - u16 state_save; + u32 state_save; uint8_t i; struct southbridge_amd_sr5650_config *cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info; - u16 state = cfg->port_enable; + u32 state = cfg->port_enable; if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS)) state &= AtiPcieCfg.PortDetect; -- cgit v1.2.3