From f1b58b78351d7ed220673e688a2f7bc9e96da4e2 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Fri, 1 Mar 2019 13:43:02 +0200
Subject: device/pci: Fix PCI accessor headers
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

PCI config accessors are no longer indirectly included
from <arch/io.h> use <device/pci_ops.h> instead.

Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
---
 src/southbridge/amd/agesa/hudson/bootblock.c   | 1 +
 src/southbridge/amd/agesa/hudson/early_setup.c | 1 +
 src/southbridge/amd/agesa/hudson/reset.c       | 1 +
 src/southbridge/amd/amd8111/amd8111.c          | 1 +
 src/southbridge/amd/amd8111/bootblock.c        | 1 +
 src/southbridge/amd/amd8111/early_smbus.c      | 1 +
 src/southbridge/amd/amd8111/reset.c            | 1 +
 src/southbridge/amd/cimx/sb800/bootblock.c     | 1 +
 src/southbridge/amd/cimx/sb800/fan.c           | 1 +
 src/southbridge/amd/cimx/sb800/late.c          | 1 +
 src/southbridge/amd/cimx/sb800/lpc.c           | 1 +
 src/southbridge/amd/cimx/sb800/reset.c         | 1 +
 src/southbridge/amd/cimx/sb900/bootblock.c     | 1 +
 src/southbridge/amd/cimx/sb900/lpc.c           | 1 +
 src/southbridge/amd/cimx/sb900/reset.c         | 1 +
 src/southbridge/amd/common/amd_pci_util.c      | 1 +
 src/southbridge/amd/pi/hudson/bootblock.c      | 1 +
 src/southbridge/amd/pi/hudson/early_setup.c    | 1 +
 src/southbridge/amd/pi/hudson/imc.c            | 1 +
 src/southbridge/amd/pi/hudson/reset.c          | 1 +
 src/southbridge/amd/rs780/early_setup.c        | 1 +
 src/southbridge/amd/sb700/bootblock.c          | 1 +
 src/southbridge/amd/sb700/early_setup.c        | 1 +
 src/southbridge/amd/sb700/reset.c              | 1 +
 src/southbridge/amd/sb700/sb700.h              | 1 +
 src/southbridge/amd/sb800/bootblock.c          | 1 +
 src/southbridge/amd/sr5650/cmn.h               | 1 +
 src/southbridge/amd/sr5650/early_setup.c       | 1 +
 28 files changed, 28 insertions(+)

(limited to 'src/southbridge/amd')

diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c
index bb6a54ba42..a10068701c 100644
--- a/src/southbridge/amd/agesa/hudson/bootblock.c
+++ b/src/southbridge/amd/agesa/hudson/bootblock.c
@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c
index af0cb58f6c..622931520f 100644
--- a/src/southbridge/amd/agesa/hudson/early_setup.c
+++ b/src/southbridge/amd/agesa/hudson/early_setup.c
@@ -18,6 +18,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <reset.h>
diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c
index 83eaa46bb4..64f947eb67 100644
--- a/src/southbridge/amd/agesa/hudson/reset.c
+++ b/src/southbridge/amd/agesa/hudson/reset.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>
 
diff --git a/src/southbridge/amd/amd8111/amd8111.c b/src/southbridge/amd/amd8111/amd8111.c
index fae22ada3b..cbf0d30859 100644
--- a/src/southbridge/amd/amd8111/amd8111.c
+++ b/src/southbridge/amd/amd8111/amd8111.c
@@ -13,6 +13,7 @@
 
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include "amd8111.h"
 
diff --git a/src/southbridge/amd/amd8111/bootblock.c b/src/southbridge/amd/amd8111/bootblock.c
index 0abd999efe..90ba000172 100644
--- a/src/southbridge/amd/amd8111/bootblock.c
+++ b/src/southbridge/amd/amd8111/bootblock.c
@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <device/pci_type.h>
 
diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c
index 4925c86abe..15a03f5306 100644
--- a/src/southbridge/amd/amd8111/early_smbus.c
+++ b/src/southbridge/amd/amd8111/early_smbus.c
@@ -11,6 +11,7 @@
  * GNU General Public License for more details.
  */
 
+#include <device/pci_ops.h>
 #include "amd8111_smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
diff --git a/src/southbridge/amd/amd8111/reset.c b/src/southbridge/amd/amd8111/reset.c
index 62ae99e414..e1ac8a98ed 100644
--- a/src/southbridge/amd/amd8111/reset.c
+++ b/src/southbridge/amd/amd8111/reset.c
@@ -15,6 +15,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <reset.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c
index 585d5a8f87..dae8df8288 100644
--- a/src/southbridge/amd/cimx/sb800/bootblock.c
+++ b/src/southbridge/amd/cimx/sb800/bootblock.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 static void enable_rom(void)
 {
diff --git a/src/southbridge/amd/cimx/sb800/fan.c b/src/southbridge/amd/cimx/sb800/fan.c
index db87b6ac87..a8dfa31d9a 100644
--- a/src/southbridge/amd/cimx/sb800/fan.c
+++ b/src/southbridge/amd/cimx/sb800/fan.c
@@ -16,6 +16,7 @@
 #include <southbridge/amd/cimx/cimx_util.h>
 #include <device/device.h>
 #include <device/pci.h>		/* device_operations */
+#include <device/pci_ops.h>
 #include "SBPLATFORM.h"
 #include "sb_cimx.h"
 #include "chip.h"		/* struct southbridge_amd_cimx_sb800_config */
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index c66206f55c..872e045a1d 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -17,6 +17,7 @@
 
 #include <device/device.h>
 #include <device/pci.h>		/* device_operations */
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 #include <bootstate.h>
 #include <arch/ioapic.h>
diff --git a/src/southbridge/amd/cimx/sb800/lpc.c b/src/southbridge/amd/cimx/sb800/lpc.c
index 2759af6488..8573f6fafe 100644
--- a/src/southbridge/amd/cimx/sb800/lpc.c
+++ b/src/southbridge/amd/cimx/sb800/lpc.c
@@ -20,6 +20,7 @@
 #include <arch/ioapic.h>
 #include "lpc.h"
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 void lpc_read_resources(struct device *dev)
 {
diff --git a/src/southbridge/amd/cimx/sb800/reset.c b/src/southbridge/amd/cimx/sb800/reset.c
index db0aebb9ee..4b96d3c8c0 100644
--- a/src/southbridge/amd/cimx/sb800/reset.c
+++ b/src/southbridge/amd/cimx/sb800/reset.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>
 
diff --git a/src/southbridge/amd/cimx/sb900/bootblock.c b/src/southbridge/amd/cimx/sb900/bootblock.c
index a06946352c..734cc7a831 100644
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -14,6 +14,7 @@
  */
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 static void sb900_enable_rom(void)
 {
diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c
index 64b6aa51de..b04ecfa123 100644
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
@@ -14,6 +14,7 @@
  */
 
 #include <device/pci.h>
+#include <device/pci_ops.h>
 #include "lpc.h"
 #include <console/console.h>	/* printk */
 #include <arch/ioapic.h>
diff --git a/src/southbridge/amd/cimx/sb900/reset.c b/src/southbridge/amd/cimx/sb900/reset.c
index db0aebb9ee..4b96d3c8c0 100644
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>
 
diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c
index ca76809bf3..8bb2e0e4ef 100644
--- a/src/southbridge/amd/common/amd_pci_util.c
+++ b/src/southbridge/amd/common/amd_pci_util.c
@@ -16,6 +16,7 @@
 #include <console/console.h>
 #include <device/pci.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <string.h>
 #include "amd_pci_util.h"
 #include <pc80/i8259.h>
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index 32b129862d..0f5bdb142b 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/pci_ids.h>
 
 /*
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 3b91f9b813..0bed6ad17e 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -19,6 +19,7 @@
 #include <assert.h>
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <reset.h>
diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c
index bb630149b8..4b41ab5749 100644
--- a/src/southbridge/amd/pi/hudson/imc.c
+++ b/src/southbridge/amd/pi/hudson/imc.c
@@ -17,6 +17,7 @@
 
 #include "imc.h"
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <device/device.h>
 #include <delay.h>
 #include <Porting.h>
diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c
index 83eaa46bb4..64f947eb67 100644
--- a/src/southbridge/amd/pi/hudson/reset.c
+++ b/src/southbridge/amd/pi/hudson/reset.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <cf9_reset.h>
 #include <reset.h>
 
diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c
index 017c76470a..0332f2f872 100644
--- a/src/southbridge/amd/rs780/early_setup.c
+++ b/src/southbridge/amd/rs780/early_setup.c
@@ -15,6 +15,7 @@
 
 #include <types.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <northbridge/amd/amdmct/mct/mct_d.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index 364fa01c51..ed6f2561f5 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -16,6 +16,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 #define IO_MEM_PORT_DECODE_ENABLE_5	0x48
 #define IO_MEM_PORT_DECODE_ENABLE_6	0x4a
diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c
index 167986fa67..af2b6c1bce 100644
--- a/src/southbridge/amd/sb700/early_setup.c
+++ b/src/southbridge/amd/sb700/early_setup.c
@@ -20,6 +20,7 @@
 #include <stdint.h>
 #include <option.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <device/pci.h>
diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c
index 4c9b0f4056..9a04459799 100644
--- a/src/southbridge/amd/sb700/reset.c
+++ b/src/southbridge/amd/sb700/reset.c
@@ -17,6 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <reset.h>
 #include <southbridge/amd/common/reset.h>
 
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 0b638f65c4..156522e579 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -73,6 +73,7 @@ void sb7xx_51xx_before_pci_init(void);
 uint16_t sb7xx_51xx_decode_last_reset(void);
 #else
 #include <device/pci.h>
+#include <device/pci_ops.h>
 /* allow override in mainboard.c */
 void sb7xx_51xx_setup_sata_phys(struct device *dev);
 void sb7xx_51xx_setup_sata_port_indication(void *sata_bar5);
diff --git a/src/southbridge/amd/sb800/bootblock.c b/src/southbridge/amd/sb800/bootblock.c
index b08d4775c4..9062118a90 100644
--- a/src/southbridge/amd/sb800/bootblock.c
+++ b/src/southbridge/amd/sb800/bootblock.c
@@ -15,6 +15,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h
index 126b786246..30aeed25d6 100644
--- a/src/southbridge/amd/sr5650/cmn.h
+++ b/src/southbridge/amd/sr5650/cmn.h
@@ -18,6 +18,7 @@
 #define __SR5650_CMN_H__
 
 #include <arch/io.h>
+#include <device/pci_ops.h>
 
 #define NBMISC_INDEX	0x60
 #define NBHTIU_INDEX	0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c
index 8b6f22a793..8671882a9f 100644
--- a/src/southbridge/amd/sr5650/early_setup.c
+++ b/src/southbridge/amd/sr5650/early_setup.c
@@ -18,6 +18,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <device/pci_ops.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
-- 
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