From eb7e6b5c8160f5edfda1ac080ab77c1ba2c48306 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 15 Jan 2018 17:52:58 +0200 Subject: amd/torpedo cimx/sb900: Fix include directory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ie472092f8926231f4e1bd1fb12839b532b4ad158 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/23279 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/southbridge/amd/cimx/sb900/gpio_oem.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'src/southbridge/amd') diff --git a/src/southbridge/amd/cimx/sb900/gpio_oem.h b/src/southbridge/amd/cimx/sb900/gpio_oem.h index b6bde9fdd5..f3ab5586a7 100644 --- a/src/southbridge/amd/cimx/sb900/gpio_oem.h +++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h @@ -3,7 +3,7 @@ /* Hudson-2 ACPI PmIO Space Define */ #define SB_ACPI_BASE_ADDRESS 0x0400 -#define ACPI_MMIO_BASE ((u8 *)0xFED80000) +#define VACPI_MMIO_BASE ((u8 *)0xFED80000) #define SB_CFG_BASE 0x000 // DWORD #define GPIO_BASE 0x100 // BYTE #define SMI_BASE 0x200 // DWORD @@ -43,4 +43,11 @@ #define Mmio32( BaseAddr, Register ) \ *Mmio32Ptr( BaseAddr, Register ) +#define SB_GPIO_REG01 1 +#define SB_GPIO_REG02 2 +#define SB_GPIO_REG15 15 +#define SB_GPIO_REG24 24 +#define SB_GPIO_REG25 25 +#define SB_GPIO_REG27 27 + #endif -- cgit v1.2.3