From b0f1988f893bf5f581917816b11e810309955143 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 9 Jun 2018 11:59:00 +0200 Subject: src: Get rid of unneeded whitespace Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/26991 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/southbridge/amd/agesa/hudson/resume.c | 4 ++-- src/southbridge/amd/cimx/sb800/acpi/fch.asl | 8 ++++---- src/southbridge/amd/cimx/sb800/late.c | 12 ++++++------ src/southbridge/amd/cimx/sb900/late.c | 18 +++++++++--------- src/southbridge/amd/cs5536/cs5536.c | 2 +- src/southbridge/amd/cs5536/cs5536.h | 2 +- src/southbridge/amd/pi/hudson/amd_pci_int_defs.h | 2 +- src/southbridge/amd/pi/hudson/early_setup.c | 2 +- src/southbridge/amd/pi/hudson/hudson.h | 8 ++++---- src/southbridge/amd/rs780/early_setup.c | 2 +- src/southbridge/amd/rs780/gfx.c | 8 ++++---- src/southbridge/amd/rs780/rs780.c | 2 +- src/southbridge/amd/rs780/rs780.h | 8 ++++---- src/southbridge/amd/sb700/sm.c | 2 +- src/southbridge/amd/sb700/usb.c | 18 +++++++++--------- src/southbridge/amd/sb800/usb.c | 18 +++++++++--------- src/southbridge/amd/sr5650/cmn.h | 12 ++++++------ src/southbridge/amd/sr5650/pcie.c | 6 +++--- src/southbridge/amd/sr5650/sr5650.c | 4 ++-- 19 files changed, 69 insertions(+), 69 deletions(-) (limited to 'src/southbridge/amd') diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index 2528294a7d..84a55430c9 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -104,8 +104,8 @@ static void s3_resume_init_data(FCH_DATA_BLOCK *FchParams) FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; - FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; + FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; #if DUMP_FCH_SETTING int i; diff --git a/src/southbridge/amd/cimx/sb800/acpi/fch.asl b/src/southbridge/amd/cimx/sb800/acpi/fch.asl index 816988b53e..6f0826fee4 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/fch.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/fch.asl @@ -178,7 +178,7 @@ Method(_INI, 0) { /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */ @@ -298,9 +298,9 @@ Scope(\){ PWMK, 1, PWNS, 1, - /* Offset(0x61), */ /* Options_1 */ - /* ,7, */ - /* R617,1, */ + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ Offset(0x65), /* UsbPMControl */ , 4, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index ebc6ba1f8d..29a1336f13 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -28,7 +28,7 @@ #include #include #include "lpc.h" /* lpc_read_resources */ -#include "SBPLATFORM.h" /* Platform Specific Definitions */ +#include "SBPLATFORM.h" /* Platform Specific Definitions */ #include "cfg.h" /* sb800 Cimx configuration */ #include "chip.h" /* struct southbridge_amd_cimx_sb800_config */ #include "sb_cimx.h" /* AMD CIMX wrapper entries */ @@ -352,13 +352,13 @@ static void sb800_enable(struct device *dev) switch (dev->path.pci.devfn) { case PCI_DEVFN(0x11, 0): /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; + sb_config->SATAMODE.SataMode.SataController = CIMX_OPTION_DISABLED; } break; @@ -387,11 +387,11 @@ static void sb800_enable(struct device *dev) case PCI_DEVFN(0x14, 2): /* 0:14:2 HDA */ if (dev->enabled) { - if (AZALIA_DISABLE == sb_config->AzaliaController) { - sb_config->AzaliaController = AZALIA_AUTO; + if (AZALIA_DISABLE == sb_config->AzaliaController) { + sb_config->AzaliaController = AZALIA_AUTO; } } else { - sb_config->AzaliaController = AZALIA_DISABLE; + sb_config->AzaliaController = AZALIA_DISABLE; } break; diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index e792fe3c61..158e3f4a1e 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -25,8 +25,8 @@ #include #include #include "lpc.h" /* lpc_read_resources */ -#include "SbPlatform.h" /* Platform Specific Definitions */ -#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ +#include "SbPlatform.h" /* Platform Specific Definitions */ +#include "chip.h" /* struct southbridge_amd_cimx_sb900_config */ #ifndef _RAMSTAGE_ #define _RAMSTAGE_ @@ -353,13 +353,13 @@ static void sb900_enable(struct device *dev) case (0x11 << 3) | 0: /* 0:11.0 SATA */ if (dev->enabled) { - sb_config->SATAMODE.SataMode.SataController = ENABLED; + sb_config->SATAMODE.SataMode.SataController = ENABLED; if (1 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary. else if (0 == sb_chip->boot_switch_sata_ide) sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary. } else { - sb_config->SATAMODE.SataMode.SataController = DISABLED; + sb_config->SATAMODE.SataMode.SataController = DISABLED; } //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY @@ -380,19 +380,19 @@ static void sb900_enable(struct device *dev) if (dev->enabled) { sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED; } else { - sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; + sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED; } //- sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY break; case (0x14 << 3) | 2: /* 0:14:2 HDA */ if (dev->enabled) { - if (AZALIA_DISABLE == sb_config->AzaliaController) { - sb_config->AzaliaController = AZALIA_AUTO; + if (sb_config->AzaliaController == AZALIA_DISABLE) { + sb_config->AzaliaController = AZALIA_AUTO; } printk(BIOS_DEBUG, "hda enabled\n"); } else { - sb_config->AzaliaController = AZALIA_DISABLE; + sb_config->AzaliaController = AZALIA_DISABLE; printk(BIOS_DEBUG, "hda disabled\n"); } //- azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio @@ -446,7 +446,7 @@ static void sb900_enable(struct device *dev) /* Special setting ABCFG registers before PCI emulation. */ //- abSpecialSetBeforePciEnum(sb_config); -//- usbDesertPll(sb_config); +//- usbDesertPll(sb_config); //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; //AmdSbDispatcher(sb_config); } diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 5f20c12843..956994d623 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -514,7 +514,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) /**************************************************************************** * - * ChipsetInit + * ChipsetInit * * Called from northbridge init (Pre-VSA). * diff --git a/src/southbridge/amd/cs5536/cs5536.h b/src/southbridge/amd/cs5536/cs5536.h index 72dbd5c216..4083f4f4eb 100644 --- a/src/southbridge/amd/cs5536/cs5536.h +++ b/src/southbridge/amd/cs5536/cs5536.h @@ -413,7 +413,7 @@ /* FLASH device macros */ #define FLASH_TYPE_NONE 0 /* No flash device installed */ -#define FLASH_TYPE_NAND 1 /* NAND device */ +#define FLASH_TYPE_NAND 1 /* NAND device */ #define FLASH_TYPE_NOR 2 /* NOR device */ #define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */ diff --git a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h index 679f233f02..1b5326b88e 100644 --- a/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h +++ b/src/southbridge/amd/pi/hudson/amd_pci_int_defs.h @@ -46,7 +46,7 @@ #define PIRQ_FC 0x14 /* FC */ #define PIRQ_GEC 0x15 /* GEC */ #define PIRQ_PMON 0x16 /* Performance Monitor */ -#define PIRQ_SD 0x17 /* SD */ +#define PIRQ_SD 0x17 /* SD */ #define PIRQ_IMC0 0x20 /* IMC INT0 */ #define PIRQ_IMC1 0x21 /* IMC INT1 */ #define PIRQ_IMC2 0x22 /* IMC INT2 */ diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index d95385be1e..b5a86dc959 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -163,7 +163,7 @@ static void enable_wideio(uint8_t port, uint16_t size) tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); tmp |= alt_wideio_enable[port]; pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); - } else { /* 512 */ + } else { /* 512 */ tmp = pci_read_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE); tmp &= ~alt_wideio_enable[port]; pci_write_config32(dev, LPC_ALT_WIDEIO_RANGE_ENABLE, tmp); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 091464f14d..922c608a67 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -121,7 +121,7 @@ #define LPC_WIDEIO2_GENERIC_PORT 0x90 -#define SPI_CNTRL0 0x00 +#define SPI_CNTRL0 0x00 #define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) /* Nominal is 16.7MHz on older devices, 33MHz on newer */ #define SPI_READ_MODE_NOM 0x00000000 @@ -137,7 +137,7 @@ #define SPI_CNTRL1 0x0c /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ -#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) +#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) #define SPI_NORM_SPEED_SH 12 #define SPI_FAST_SPEED_SH 8 @@ -153,10 +153,10 @@ #define SPI_SPEED_800K (BIT(2) | BIT(0)) #define SPI_NORM_SPEED_NEW_SH 12 #define SPI_FAST_SPEED_NEW_SH 8 -#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_ALT_SPEED_NEW_SH 4 #define SPI_TPM_SPEED_NEW_SH 0 -#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI100_HOST_PREF_CONFIG 0x2c #define SPI_RD4DW_EN_HOST BIT(15) static inline int hudson_sata_enable(void) diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index 7bc9435b5b..ab75e5f57f 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -24,7 +24,7 @@ #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ #define NBMISC_INDEX 0x60 -#define NBMC_INDEX 0xE8 +#define NBMC_INDEX 0xE8 static u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index) { diff --git a/src/southbridge/amd/rs780/gfx.c b/src/southbridge/amd/rs780/gfx.c index cfcddb29f3..30345bef11 100644 --- a/src/southbridge/amd/rs780/gfx.c +++ b/src/southbridge/amd/rs780/gfx.c @@ -186,7 +186,7 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) printk(BIOS_DEBUG, "Dev ID %x\n", Value); if ((Value & 0xffff) == 0x1102) {//Creative //Found Creative SB - u32 MMIOStart = 0xffffffff; + u32 MMIOStart = 0xffffffff; u32 MMIOLimit = 0; for (Reg = 0x10; Reg < 0x20; Reg+=4) { u32 BaseA, LimitA; @@ -449,7 +449,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.ulMinSidePortClock = 333*100; #endif - vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default + vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default // find the DDR memory frequency if (is_family10h()) { @@ -1109,8 +1109,8 @@ static void dual_port_configuration(struct device *nb_dev, struct device *dev) /* For single port GFX configuration Only * width: -* 000 = x16 -* 001 = x1 +* 000 = x16 +* 001 = x1 * 010 = x2 * 011 = x4 * 100 = x8 diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index ef40ffd060..f4f33efab7 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -93,7 +93,7 @@ void static rs780_config_misc_clk(struct device *nb_dev) byte |= 1 << 0; pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); - /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ + /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ /* TODO: */ #endif diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index ce46d96760..e96608eba9 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -22,10 +22,10 @@ #include "chip.h" #include "rev.h" -#define NBMISC_INDEX 0x60 -#define NBHTIU_INDEX 0x94 -#define NBMC_INDEX 0xE8 -#define NBPCIE_INDEX 0xE0 +#define NBMISC_INDEX 0x60 +#define NBHTIU_INDEX 0x94 +#define NBMC_INDEX 0xE8 +#define NBPCIE_INDEX 0xE0 #define EXT_CONF_BASE_ADDRESS 0xE0000000 #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6211ddeec2..64c6db3072 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -225,7 +225,7 @@ static void sm_init(struct device *dev) pci_write_config8(dev, 0xE1, byte); /* 2.5 Enabling Non-Posted Memory Write */ - axindxc_reg(0x10, 1 << 9, 1 << 9); + axindxc_reg(0x10, 1 << 9, 1 << 9); /* 2.11 IO Trap Settings */ abcfg_reg(0x10090, 1 << 16, 1 << 16); diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index 12b9dd673a..bf790565ee 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -215,14 +215,14 @@ static const struct pci_driver usb_1_driver __pci_driver = { /* the pci id of usb ctrl 0 and 1 are the same. */ /* * static const struct pci_driver usb_3_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_0, + * .ops = &usb_ops, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_0, * }; * static const struct pci_driver usb_4_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_1, + * .ops = &usb_ops, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_1, * }; */ @@ -248,8 +248,8 @@ static const struct pci_driver usb_5_driver __pci_driver = { }; /* * static const struct pci_driver usb_5_driver __pci_driver = { - * .ops = &usb_ops2, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_2, + * .ops = &usb_ops2, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB700_USB_19_2, * }; */ diff --git a/src/southbridge/amd/sb800/usb.c b/src/southbridge/amd/sb800/usb.c index 2318a8ff8f..715095f443 100644 --- a/src/southbridge/amd/sb800/usb.c +++ b/src/southbridge/amd/sb800/usb.c @@ -166,14 +166,14 @@ static const struct pci_driver usb_1_driver __pci_driver = { /* the pci id of usb ctrl 0 and 1 are the same. */ /* * static const struct pci_driver usb_3_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_0, + * .ops = &usb_ops, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_0, * }; * static const struct pci_driver usb_4_driver __pci_driver = { - * .ops = &usb_ops, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_1, + * .ops = &usb_ops, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_1, * }; */ @@ -199,8 +199,8 @@ static const struct pci_driver usb_5_driver __pci_driver = { }; /* * static const struct pci_driver usb_5_driver __pci_driver = { - * .ops = &usb_ops2, - * .vendor = PCI_VENDOR_ID_ATI, - * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_2, + * .ops = &usb_ops2, + * .vendor = PCI_VENDOR_ID_ATI, + * .device = PCI_DEVICE_ID_ATI_SB800_USB_19_2, * }; */ diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index e44d1e89c0..859e15dd62 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -19,12 +19,12 @@ #include -#define NBMISC_INDEX 0x60 -#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ -#define NBMC_INDEX 0xE8 -#define NBPCIE_INDEX 0xE0 -#define L2CFG_INDEX 0xF0 -#define L1CFG_INDEX 0xF8 +#define NBMISC_INDEX 0x60 +#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ +#define NBMC_INDEX 0xE8 +#define NBPCIE_INDEX 0xE0 +#define L2CFG_INDEX 0xF0 +#define L1CFG_INDEX 0xF8 #define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 9e2bd9233e..8986e676dc 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -454,14 +454,14 @@ static void EnableLclkGating(struct device *dev) reg = 0xE8; port = dev->path.pci.devfn >> 3; switch (port) { - //PCIE_CORE_INDEX_GPP1 + //PCIE_CORE_INDEX_GPP1 case 2: case 3: reg = 0x94; mask = 1 << 16; break; - //PCIE_CORE_INDEX_GPP2 + //PCIE_CORE_INDEX_GPP2 case 11: case 12: value = 1 << 28; @@ -479,7 +479,7 @@ static void EnableLclkGating(struct device *dev) value = 1 << 25; break; - //PCIE_CORE_INDEX_SB; + //PCIE_CORE_INDEX_SB; case 8: reg = 0x94; mask = 1 << 24; diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 1962ea3277..fae26899ec 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -427,7 +427,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) { dword |= (0x1 << 0); l2cfg_ind_write_index(nb_dev, 0x44, dword); -// if (get_nb_rev(nb_dev) == REV_SR5650_A21) { +// if (get_nb_rev(nb_dev) == REV_SR5650_A21) { dword = l2cfg_ind_read_index(nb_dev, 0x7); dword |= (0x1 << 1); l2cfg_ind_write_index(nb_dev, 0x7, dword); @@ -479,7 +479,7 @@ void detect_and_enable_iommu(struct device *iommu_dev) { dword = l2cfg_ind_read_index(nb_dev, 0x6); dword |= (0x1 << 8); l2cfg_ind_write_index(nb_dev, 0x6, dword); -// } +// } l2cfg_ind_write_index(nb_dev, 0x52, 0xf0000002); -- cgit v1.2.3