From 9fe4d797a37671a65053add3f7cca27397db0b9b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 16 Jan 2010 17:53:38 +0000 Subject: coreboot used to have two different "APIs" for memory accesses: read32(unsigned long addr) vs readl(void *addr) and write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr) read32 was only available in __PRE_RAM__ stage, while readl was used in stage2. Some unclean implementations then made readl available to __PRE_RAM__ too which results in really messy includes and code. This patch fixes all code to use the read32/write32 variant, so that we can remove readl/writel in another patch. Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/amd8111/amd8111_nic.c | 6 ++-- src/southbridge/amd/cs5530/cs5530_vga.c | 54 +++++++++++++++---------------- src/southbridge/amd/cs5536/cs5536.c | 22 ++++++------- src/southbridge/amd/sb600/sb600_hda.c | 18 +++++------ src/southbridge/amd/sb600/sb600_sata.c | 24 +++++++------- src/southbridge/amd/sb600/sb600_usb.c | 8 ++--- 6 files changed, 66 insertions(+), 66 deletions(-) (limited to 'src/southbridge/amd') diff --git a/src/southbridge/amd/amd8111/amd8111_nic.c b/src/southbridge/amd/amd8111/amd8111_nic.c index d326d83dda..98ac62b5d7 100644 --- a/src/southbridge/amd/amd8111/amd8111_nic.c +++ b/src/southbridge/amd/amd8111/amd8111_nic.c @@ -54,12 +54,12 @@ static void nic_init(struct device *dev) /* Hard Reset PHY */ printk_debug("Reseting PHY... "); if (conf->phy_lowreset) { - writel(VAL0 | PHY_RST_POL | RESET_PHY , (void *)(mmio + CMD3)); + write32((void *)(mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { - writel(VAL0 | RESET_PHY, (void *)(mmio + CMD3)); + write32((void *)(mmio + CMD3), VAL0 | RESET_PHY); } mdelay(15); - writel(RESET_PHY, (void *)(mmio + CMD3)); + write32((void *)(mmio + CMD3), RESET_PHY); printk_debug("Done\n"); } diff --git a/src/southbridge/amd/cs5530/cs5530_vga.c b/src/southbridge/amd/cs5530/cs5530_vga.c index 2dc8cf0b3b..b5182590d5 100644 --- a/src/southbridge/amd/cs5530/cs5530_vga.c +++ b/src/southbridge/amd/cs5530/cs5530_vga.c @@ -242,27 +242,27 @@ static void cs5530_set_clock_frequency(void *io_base, unsigned long pll_val) unsigned long reg; /* disable the PLL first, reset and power it down */ - reg = readl(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20; + reg = read32(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20; reg |= 0x80000100; - writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + write32(io_base+CS5530_DOT_CLK_CONFIG, reg); /* write the new PLL setting */ reg |= (pll_val & ~0x80000920); - writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + write32(io_base+CS5530_DOT_CLK_CONFIG, reg); mdelay(1); /* wait for control voltage to be 0V */ /* enable the PLL */ reg |= 0x00000800; - writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + write32(io_base+CS5530_DOT_CLK_CONFIG, reg); /* clear reset */ reg &= ~0x80000000; - writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + write32(io_base+CS5530_DOT_CLK_CONFIG, reg); /* clear bypass */ reg &= ~0x00000100; - writel(reg, io_base+CS5530_DOT_CLK_CONFIG); + write32(io_base+CS5530_DOT_CLK_CONFIG, reg); } /** @@ -286,15 +286,15 @@ static void dc_setup_layout(void *gx_base, const struct video_mode *mode) { u32 base = 0x00000000; - writel(base, gx_base + DC_FB_ST_OFFSET); + write32(gx_base + DC_FB_ST_OFFSET, base); base += (COLOUR_DEPTH>>3) * mode->visible_pixel * mode->visible_lines; - writel(base, gx_base + DC_CB_ST_OFFSET); - writel(base, gx_base + DC_CURS_ST_OFFSET); - writel(base, gx_base + DC_VID_ST_OFFSET); - writel(((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2, gx_base + DC_LINE_DELTA); - writel(((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3, gx_base + DC_BUF_SIZE); + write32(gx_base + DC_CB_ST_OFFSET, base); + write32(gx_base + DC_CURS_ST_OFFSET, base); + write32(gx_base + DC_VID_ST_OFFSET, base); + write32(gx_base + DC_LINE_DELTA, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2); + write32(gx_base + DC_BUF_SIZE, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3); } /** @@ -343,20 +343,20 @@ static void dc_setup_timing(void *gx_base, const struct video_mode *mode) vtotal = vblankend; /* row description */ - writel((hactive - 1) | ((htotal - 1) << 16), gx_base + DC_H_TIMING_1); + write32(gx_base + DC_H_TIMING_1, (hactive - 1) | ((htotal - 1) << 16)); /* horizontal blank description */ - writel((hblankstart - 1) | ((hblankend - 1) << 16), gx_base + DC_H_TIMING_2); + write32(gx_base + DC_H_TIMING_2, (hblankstart - 1) | ((hblankend - 1) << 16)); /* horizontal sync description */ - writel((hsyncstart - 1) | ((hsyncend - 1) << 16), gx_base + DC_H_TIMING_3); - writel((hsyncstart - 1) | ((hsyncend - 1) << 16), gx_base + DC_FP_H_TIMING); + write32(gx_base + DC_H_TIMING_3, (hsyncstart - 1) | ((hsyncend - 1) << 16)); + write32(gx_base + DC_FP_H_TIMING, (hsyncstart - 1) | ((hsyncend - 1) << 16)); /* line description */ - writel((vactive - 1) | ((vtotal - 1) << 16), gx_base + DC_V_TIMING_1); + write32(gx_base + DC_V_TIMING_1, (vactive - 1) | ((vtotal - 1) << 16)); /* vertical blank description */ - writel((vblankstart - 1) | ((vblankend - 1) << 16), gx_base + DC_V_TIMING_2); + write32(gx_base + DC_V_TIMING_2, (vblankstart - 1) | ((vblankend - 1) << 16)); /* vertical sync description */ - writel((vsyncstart - 1) | ((vsyncend - 1) << 16), gx_base + DC_V_TIMING_3); - writel((vsyncstart - 2) | ((vsyncend - 2) << 16), gx_base + DC_FP_V_TIMING); + write32(gx_base + DC_V_TIMING_3, (vsyncstart - 1) | ((vsyncend - 1) << 16)); + write32(gx_base + DC_FP_V_TIMING, (vsyncstart - 2) | ((vsyncend - 2) << 16)); } /** @@ -369,14 +369,14 @@ static void dc_setup_timing(void *gx_base, const struct video_mode *mode) */ static void cs5530_activate_mode(void *gx_base, const struct video_mode *mode) { - writel(0x00000080, gx_base + DC_GENERAL_CFG); + write32(gx_base + DC_GENERAL_CFG, 0x00000080); mdelay(1); dc_setup_layout(gx_base,mode); dc_setup_timing(gx_base,mode); - writel(0x2000C581, gx_base + DC_GENERAL_CFG); - writel(0x0000002F, gx_base + DC_TIMING_CFG); - writel(0x00003004, gx_base + DC_OUTPUT_CFG); + write32(gx_base + DC_GENERAL_CFG, 0x2000C581); + write32(gx_base + DC_TIMING_CFG, 0x0000002F); + write32(gx_base + DC_OUTPUT_CFG, 0x00003004); } /** @@ -392,7 +392,7 @@ static void cs5530_activate_video(void *io_base, const struct video_mode *mode) u32 val; val = (u32)mode->sync_pol << 8; - writel(val | 0x0020002F, io_base + CS5530_DISPLAY_CONFIG); + write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F); } #if CONFIG_SPLASH_GRAPHIC == 1 @@ -465,7 +465,7 @@ static void cs5530_vga_init(device_t dev) cs5530_set_clock_frequency(io_base, mode->pll_value); - writel(DC_UNLOCK_MAGIC, gx_base + DC_UNLOCK); + write32(gx_base + DC_UNLOCK, DC_UNLOCK_MAGIC); show_boot_splash_16(mode->visible_pixel, mode->visible_lines, mode->visible_pixel * (COLOUR_DEPTH>>3), (void*)(GX_BASE + 0x800000)); @@ -473,7 +473,7 @@ static void cs5530_vga_init(device_t dev) cs5530_activate_mode(gx_base, mode); cs5530_activate_video(io_base, mode); - writel(0x00000000, gx_base + DC_UNLOCK); + write32(gx_base + DC_UNLOCK, 0x00000000); } static struct device_operations vga_ops = { diff --git a/src/southbridge/amd/cs5536/cs5536.c b/src/southbridge/amd/cs5536/cs5536.c index 002335d6b2..89e0cf5951 100644 --- a/src/southbridge/amd/cs5536/cs5536.c +++ b/src/southbridge/amd/cs5536/cs5536.c @@ -428,10 +428,10 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); /* Make HCCPARAMS writeable */ - writel(readl(bar + IPREG04) | USB_HCCPW_SET, bar + IPREG04); + write32(bar + IPREG04, read32(bar + IPREG04) | USB_HCCPW_SET); /* ; EECP=50h, IST=01h, ASPC=1 */ - writel(0x00005012, bar + HCCPARAMS); + write32(bar + HCCPARAMS, 0x00005012); } dev = dev_find_device(PCI_VENDOR_ID_AMD, @@ -439,19 +439,19 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) if (dev) { bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - writel(readl(bar + UOCMUX) & PUEN_SET, bar + UOCMUX); + write32(bar + UOCMUX, read32(bar + UOCMUX) & PUEN_SET); /* Host or Device? */ if (sb->enable_USBP4_device) { - writel(readl(bar + UOCMUX) | PMUX_DEVICE, bar + UOCMUX); + write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_DEVICE); } else { - writel(readl(bar + UOCMUX) | PMUX_HOST, bar + UOCMUX); + write32(bar + UOCMUX, read32(bar + UOCMUX) | PMUX_HOST); } /* Overcurrent configuration */ if (sb->enable_USBP4_overcurrent) { - writel(readl(bar + UOCCAP) - | sb->enable_USBP4_overcurrent, bar + UOCCAP); + write32(bar + UOCCAP, read32(bar + UOCCAP) + | sb->enable_USBP4_overcurrent); } } @@ -467,8 +467,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) if (dev) { bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - writel(readl(bar + UDCDEVCTL) | UDC_SD_SET, - bar + UDCDEVCTL); + write32(bar + UDCDEVCTL, + read32(bar + UDCDEVCTL) | UDC_SD_SET); } @@ -477,8 +477,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb) if (dev) { bar = (uint8_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0); - writel(readl(bar + UOCCTL) | PADEN_SET, bar + UOCCTL); - writel(readl(bar + UOCCAP) | APU_SET, bar + UOCCAP); + write32(bar + UOCCTL, read32(bar + UOCCTL) | PADEN_SET); + write32(bar + UOCCAP, read32(bar + UOCCAP) | APU_SET); } } diff --git a/src/southbridge/amd/sb600/sb600_hda.c b/src/southbridge/amd/sb600/sb600_hda.c index 4c17c04bbb..3d24825c63 100644 --- a/src/southbridge/amd/sb600/sb600_hda.c +++ b/src/southbridge/amd/sb600/sb600_hda.c @@ -37,10 +37,10 @@ static int set_bits(u8 * port, u32 mask, u32 val) /* Write (val & ~mask) to port */ val &= mask; - dword = readl(port); + dword = read32(port); dword &= ~mask; dword |= val; - writel(dword, port); + write32(port, dword); /* Wait for readback of register to * match what was just written to it @@ -49,7 +49,7 @@ static int set_bits(u8 * port, u32 mask, u32 val) do { /* Wait 1ms based on BKDG wait time */ mdelay(1); - dword = readl(port); + dword = read32(port); dword &= mask; } while ((dword != val) && --count); @@ -75,7 +75,7 @@ static u32 codec_detect(u8 * base) mdelay(1); /* Read in Codec location (BAR + 0xe)[3..0]*/ - dword = readl(base + 0xe); + dword = read32(base + 0xe); dword &= 0x0F; if (!dword) goto no_codec; @@ -180,7 +180,7 @@ static int wait_for_ready(u8 *base) int timeout = 50; while(timeout--) { - u32 dword=readl(base + HDA_ICII_REG); + u32 dword=read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; udelay(1); @@ -202,7 +202,7 @@ static int wait_for_valid(u8 *base) int timeout = 50; while(timeout--) { - u32 dword = readl(base + HDA_ICII_REG); + u32 dword = read32(base + HDA_ICII_REG); if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; @@ -224,12 +224,12 @@ static void codec_init(u8 * base, int addr) return; dword = (addr << 28) | 0x000f0000; - writel(dword, base + 0x60); + write32(base + 0x60, dword); if (wait_for_valid(base) == -1) return; - dword = readl(base + 0x64); + dword = read32(base + 0x64); /* 2 */ printk_debug("codec viddid: %08x\n", dword); @@ -246,7 +246,7 @@ static void codec_init(u8 * base, int addr) if (wait_for_ready(base) == -1) return; - writel(verb[i], base + 0x60); + write32(base + 0x60, verb[i]); if (wait_for_valid(base) == -1) return; diff --git a/src/southbridge/amd/sb600/sb600_sata.c b/src/southbridge/amd/sb600/sb600_sata.c index 3d7f2c416c..b0074b70e3 100644 --- a/src/southbridge/amd/sb600/sb600_sata.c +++ b/src/southbridge/amd/sb600/sb600_sata.c @@ -172,7 +172,7 @@ static void sata_init(struct device *dev) /* Use BAR5+0x2A8,BAR2 for Secondary Slave */ for (i = 0; i < 4; i++) { - byte = readb(sata_bar5 + 0x128 + 0x80 * i); + byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk_spew("SATA port %i status = %x\n", i, byte); byte &= 0xF; @@ -182,24 +182,24 @@ static void sata_init(struct device *dev) printk_spew("SATA device detected but not talking. Trying lower speed.\n"); /* Read in Port-N Serial ATA Control Register */ - byte = readb(sata_bar5 + 0x12C + 0x80 * i); + byte = read8(sata_bar5 + 0x12C + 0x80 * i); /* Set Reset Bit and 1.5g bit */ byte |= 0x11; - writeb(byte, (sata_bar5 + 0x12C + 0x80 * i)); + write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Clear Reset Bit */ byte &= ~0x01; - writeb(byte, (sata_bar5 + 0x12C + 0x80 * i)); + write8((sata_bar5 + 0x12C + 0x80 * i), byte); /* Wait 1ms */ mdelay(1); /* Reread status */ - byte = readb(sata_bar5 + 0x128 + 0x80 * i); + byte = read8(sata_bar5 + 0x128 + 0x80 * i); printk_spew("SATA port %i status = %x\n", i, byte); byte &= 0xF; } @@ -223,15 +223,15 @@ static void sata_init(struct device *dev) /* Below is CIM InitSataLateFar */ /* Enable interrupts from the HBA */ - byte = readb(sata_bar5 + 0x4); + byte = read8(sata_bar5 + 0x4); byte |= 1 << 1; - writeb(byte, (sata_bar5 + 0x4)); + write8((sata_bar5 + 0x4), byte); /* Clear error status */ - writel(0xFFFFFFFF, (sata_bar5 + 0x130)); - writel(0xFFFFFFFF, (sata_bar5 + 0x1b0)); - writel(0xFFFFFFFF, (sata_bar5 + 0x230)); - writel(0xFFFFFFFF, (sata_bar5 + 0x2b0)); + write32((sata_bar5 + 0x130), 0xFFFFFFFF); + write32((sata_bar5 + 0x1b0), 0xFFFFFFFF); + write32((sata_bar5 + 0x230), 0xFFFFFFFF); + write32((sata_bar5 + 0x2b0), 0xFFFFFFFF); /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */ /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */ @@ -241,7 +241,7 @@ static void sata_init(struct device *dev) /* byte = pm_ioread(0x29); */ /* word |= byte<<8; */ /* printk_debug("AcpiGpe0Blk addr = %x\n", word); */ - /* writel(0x80000000 , word); */ + /* write32(word, 0x80000000); */ } static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/sb600/sb600_usb.c b/src/southbridge/amd/sb600/sb600_usb.c index 2002114f81..4be2d73272 100644 --- a/src/southbridge/amd/sb600/sb600_usb.c +++ b/src/southbridge/amd/sb600/sb600_usb.c @@ -98,16 +98,16 @@ static void usb_init2(struct device *dev) /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ dword = 0x00020F00; - writel(dword, usb2_bar0 + 0xC0); + write32(usb2_bar0 + 0xC0, dword); /* RPR5.5 Sets In/OUT FIFO threshold for best performance */ dword = 0x00200040; - writel(dword, usb2_bar0 + 0xA4); + write32(usb2_bar0 + 0xA4, dword); /* RPR5.9 Disable the EHCI Dynamic Power Saving feature */ - word = readl(usb2_bar0 + 0xBC); + word = read16(usb2_bar0 + 0xBC); word &= ~(1 << 12); - writew(word, usb2_bar0 + 0xBC); + write16(usb2_bar0 + 0xBC, word); /* RPR5.10 Disable EHCI MSI support */ byte = pci_read_config8(dev, 0x50); -- cgit v1.2.3