From 78c5d584a087265e44b076647db19efd4db4a7bb Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 9 Jan 2015 23:48:47 +0200 Subject: ACPI: Add acpi_is_wakeup_s3() for romstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This replaces acpi_is_wakeup_early(). Change-Id: I23112c1fc7b6f99584bc065fbf6b10fb073b1eb6 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8187 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan --- src/southbridge/amd/agesa/hudson/Makefile.inc | 4 +- src/southbridge/amd/agesa/hudson/early_setup.c | 28 ------------ src/southbridge/amd/agesa/hudson/hudson.c | 40 ----------------- src/southbridge/amd/agesa/hudson/ramtop.c | 59 ++++++++++++++++++++++++++ src/southbridge/amd/cimx/sb800/Makefile.inc | 3 ++ src/southbridge/amd/cimx/sb800/cfg.c | 47 +------------------- src/southbridge/amd/cimx/sb800/early.c | 8 ---- src/southbridge/amd/cimx/sb800/ramtop.c | 59 ++++++++++++++++++++++++++ src/southbridge/amd/sb700/early_setup.c | 9 ++-- src/southbridge/amd/sb700/lpc.c | 17 +++----- src/southbridge/amd/sb800/early_setup.c | 9 ++-- 11 files changed, 137 insertions(+), 146 deletions(-) create mode 100644 src/southbridge/amd/agesa/hudson/ramtop.c create mode 100644 src/southbridge/amd/cimx/sb800/ramtop.c (limited to 'src/southbridge/amd') diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 84f0d3ecc0..bcadd8ddfd 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -19,7 +19,9 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-y += resume.c +ramstage-y += resume.c ramtop.c + +romstage-y += ramtop.c romstage-y += imc.c ramstage-y += imc.c diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 1b9b6891e8..381614135a 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -123,32 +123,4 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} - -int acpi_is_wakeup_early(void) -{ - return (acpi_get_sleep_type() == 3); -} -#endif /* CONFIG_HAVE_ACPI_RESUME */ - -unsigned long get_top_of_ram(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} - #endif /* _HUDSON_EARLY_SETUP_C_ */ diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index be8aa69264..fd2c268a23 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -38,30 +38,6 @@ */ #define PM_MMIO_BASE 0xfed80300 - -#if CONFIG_HAVE_ACPI_RESUME -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} -#endif - -void backup_top_of_ram(uint64_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xf8, i; /* temp */ - /* printk(BIOS_DEBUG, "dword=%x\n", dword); */ - for (i = 0; i<4; i++) { - /* printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); */ - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); - nvram_pos++; - } -} - void pm_write8(u8 reg, u8 value) { write8(PM_MMIO_BASE + reg, value); @@ -160,22 +136,6 @@ void hudson_enable(device_t dev) } } -#if CONFIG_HAVE_ACPI_RESUME -unsigned long get_top_of_ram(void) -{ - uint32_t xdata = 0; - int xnvram_pos = 0xf8, xi; - if (acpi_get_sleep_type() != 3) - return 0; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} -#endif static void hudson_init_acpi_ports(void) { diff --git a/src/southbridge/amd/agesa/hudson/ramtop.c b/src/southbridge/amd/agesa/hudson/ramtop.c new file mode 100644 index 0000000000..182150f02e --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/ramtop.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "hudson.h" + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} + +#ifndef __PRE_RAM__ +void backup_top_of_ram(uint64_t ramtop) +{ + u32 dword = (u32) ramtop; + int nvram_pos = 0xf8, i; /* temp */ + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif + +unsigned long get_top_of_ram(void) +{ + uint32_t xdata = 0; + int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (unsigned long) xdata; +} diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index f4a84b7c22..ca3d86ab02 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc @@ -34,6 +34,9 @@ ramstage-$(CONFIG_SB800_IMC_FAN_CONTROL) += fan.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += ramtop.c + romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += ../../sb800/enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += ../../sb800/enable_usbdebug.c diff --git a/src/southbridge/amd/cimx/sb800/cfg.c b/src/southbridge/amd/cimx/sb800/cfg.c index 9ddcf8f314..ac6e6aeb81 100644 --- a/src/southbridge/amd/cimx/sb800/cfg.c +++ b/src/southbridge/amd/cimx/sb800/cfg.c @@ -26,48 +26,6 @@ #include #include -#if CONFIG_HAVE_ACPI_RESUME -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(PM1_CNT_BLK_ADDRESS); - tmp = ((tmp & (7 << 10)) >> 10); - /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ - return (int)tmp; -} -#endif - -#ifndef __PRE_RAM__ -void backup_top_of_ram(uint64_t ramtop) -{ - u32 dword = (u32) ramtop; - int nvram_pos = 0xf8, i; /* temp */ - printk(BIOS_DEBUG, "dword=%x\n", dword); - for (i = 0; i<4; i++) { - printk(BIOS_DEBUG, "nvram_pos=%x, dword>>(8*i)=%x\n", nvram_pos, (dword >>(8 * i)) & 0xff); - outb(nvram_pos, BIOSRAM_INDEX); - outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); - nvram_pos++; - } -} -#endif - -#if CONFIG_HAVE_ACPI_RESUME -unsigned long get_top_of_ram(void) -{ - u32 xdata = 0; - int xnvram_pos = 0xf8, xi; - if (acpi_get_sleep_type() != 3) - return 0; - for (xi = 0; xi<4; xi++) { - outb(xnvram_pos, BIOSRAM_INDEX); - xdata &= ~(0xff << (xi * 8)); - xdata |= inb(BIOSRAM_DATA) << (xi *8); - xnvram_pos++; - } - return (unsigned long) xdata; -} -#endif - /** * @brief South Bridge CIMx configuration * @@ -80,10 +38,7 @@ void sb800_cimx_config(AMDSBCFG *sb_config) if (!sb_config) return; -#if CONFIG_HAVE_ACPI_RESUME - if (acpi_get_sleep_type() == 3) - sb_config->S3Resume = 1; -#endif + sb_config->S3Resume = acpi_is_wakeup_s3(); /* header */ sb_config->StdHeader.PcieBasePtr = PCIEX_BASE_ADDRESS; diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 7492f9942d..34375c59e4 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -20,7 +20,6 @@ #include #include #include /* inl, outl */ -#include #include "SBPLATFORM.h" #include "sb_cimx.h" #include "cfg.h" /*sb800_cimx_config*/ @@ -74,10 +73,3 @@ void sb800_clk_output_48Mhz(void) *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */ *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */ } - -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) -{ - return (acpi_get_sleep_type() == 3); -} -#endif diff --git a/src/southbridge/amd/cimx/sb800/ramtop.c b/src/southbridge/amd/cimx/sb800/ramtop.c new file mode 100644 index 0000000000..7e9abaeced --- /dev/null +++ b/src/southbridge/amd/cimx/sb800/ramtop.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include "SBPLATFORM.h" + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} + +#ifndef __PRE_RAM__ +void backup_top_of_ram(uint64_t ramtop) +{ + u32 dword = (u32) ramtop; + int nvram_pos = 0xf8, i; /* temp */ + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif + +unsigned long get_top_of_ram(void) +{ + u32 xdata = 0; + int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (unsigned long) xdata; +} diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 82d51e6053..855cbc49be 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -721,20 +721,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) +int acpi_get_sleep_type(void) { u16 tmp; tmp = inw(ACPI_PM1_CNT_BLK); - printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); - return (((tmp & (7 << 10)) >> 10) == 3); + return ((tmp & (7 << 10)) >> 10); } unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; - if (!acpi_is_wakeup_early()) + if (acpi_get_sleep_type() != 3) return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); @@ -744,6 +742,5 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } -#endif #endif diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index 8ebc765c0b..658e95498e 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include "sb700.h" @@ -80,19 +79,15 @@ static void lpc_init(device_t dev) #endif pci_write_config8(dev, 0x78, byte); - /* hack, but the whole sb700 startup lacks any device which - is doing the acpi init */ -#if CONFIG_HAVE_ACPI_RESUME - { - u16 tmp = inw(ACPI_PM1_CNT_BLK); - acpi_slp_type = ((tmp & (7 << 10)) >> 10); - printk(BIOS_DEBUG, "SLP_TYP type was %x\n", acpi_slp_type); - } -#endif - cmos_check_update_date(); } +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + return ((tmp & (7 << 10)) >> 10); +} + void backup_top_of_ram(uint64_t ramtop) { u32 dword = (u32) ramtop; diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 2b488d937d..24aa2007a5 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -666,20 +666,18 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void) +int acpi_get_sleep_type(void) { u16 tmp; tmp = inw(ACPI_PM1_CNT_BLK); - printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); - return (((tmp & (7 << 10)) >> 10) == 3); + return ((tmp & (7 << 10)) >> 10); } unsigned long get_top_of_ram(void) { uint32_t xdata = 0; int xnvram_pos = 0xfc, xi; - if (!acpi_is_wakeup_early()) + if (acpi_get_sleep_type() != 3) return 0; for (xi = 0; xi<4; xi++) { outb(xnvram_pos, BIOSRAM_INDEX); @@ -689,6 +687,5 @@ unsigned long get_top_of_ram(void) } return (unsigned long) xdata; } -#endif #endif -- cgit v1.2.3