From 0867062412dd4bfe5a556e5f3fd85ba5b682d79b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 30 Jun 2009 15:17:49 +0000 Subject: This patch unifies the use of config options in v2 to all start with CONFIG_ It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/amd8111/amd8111_acpi.c | 10 +++++----- src/southbridge/amd/cs5530/cs5530_pirq.c | 2 +- src/southbridge/amd/cs5536/cs5536_pirq.c | 2 +- src/southbridge/amd/sb600/sb600_early_setup.c | 2 +- src/southbridge/amd/sb600/sb600_sm.c | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) (limited to 'src/southbridge/amd') diff --git a/src/southbridge/amd/amd8111/amd8111_acpi.c b/src/southbridge/amd/amd8111/amd8111_acpi.c index 57c26910f8..9511474062 100644 --- a/src/southbridge/amd/amd8111/amd8111_acpi.c +++ b/src/southbridge/amd/amd8111/amd8111_acpi.c @@ -16,8 +16,8 @@ #define SLOW_CPU_OFF 0 #define SLOW_CPU__ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif @@ -66,7 +66,7 @@ static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) return do_smbus_write_byte(res->base, device, address, val); } -#if HAVE_ACPI_TABLES == 1 +#if CONFIG_HAVE_ACPI_TABLES == 1 unsigned pm_base; #endif @@ -112,7 +112,7 @@ static void acpi_init(struct device *dev) pci_write_config8(dev, 0x41, byte | (1<<6)|(1<<5)); /* power on after power fail */ - on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pci_read_config8(dev, PREVIOUS_POWER_STATE); byte &= ~0x40; @@ -140,7 +140,7 @@ static void acpi_init(struct device *dev) (on*12)+(on>>1),(on&1)*5); } -#if HAVE_ACPI_TABLES == 1 +#if CONFIG_HAVE_ACPI_TABLES == 1 pm_base = pci_read_config16(dev, 0x58) & 0xff00; printk_debug("pm_base: 0x%04x\n",pm_base); #endif diff --git a/src/southbridge/amd/cs5530/cs5530_pirq.c b/src/southbridge/amd/cs5530/cs5530_pirq.c index edae7c9ab6..3fb9a74a1e 100644 --- a/src/southbridge/amd/cs5530/cs5530_pirq.c +++ b/src/southbridge/amd/cs5530/cs5530_pirq.c @@ -23,7 +23,7 @@ #include #include -#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1) +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1) void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; diff --git a/src/southbridge/amd/cs5536/cs5536_pirq.c b/src/southbridge/amd/cs5536/cs5536_pirq.c index b8b4a10b1d..0723253898 100644 --- a/src/southbridge/amd/cs5536/cs5536_pirq.c +++ b/src/southbridge/amd/cs5536/cs5536_pirq.c @@ -23,7 +23,7 @@ #include #include -#if (PIRQ_ROUTE==1 && HAVE_PIRQ_TABLE==1) +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_HAVE_PIRQ_TABLE==1) void pirq_assign_irqs(const unsigned char pIntAtoD[4]) { device_t pdev; diff --git a/src/southbridge/amd/sb600/sb600_early_setup.c b/src/southbridge/amd/sb600/sb600_early_setup.c index e63e8e930e..b605b5e3bf 100644 --- a/src/southbridge/amd/sb600/sb600_early_setup.c +++ b/src/southbridge/amd/sb600/sb600_early_setup.c @@ -434,7 +434,7 @@ static void sb600_devices_por_init() /*CIM set this register; but I didn't find its description in RPR. On DBM690T platform, I didn't find different between set and skip this register. - But on Filbert platform, the DEBUG message from serial port on Peanut board can't be displayed + But on Filbert platform, the CONFIG_DEBUG message from serial port on Peanut board can't be displayed after the bit0 of this register is set. pci_write_config8(dev, 0x04, 0x21); */ diff --git a/src/southbridge/amd/sb600/sb600_sm.c b/src/southbridge/amd/sb600/sb600_sm.c index a107d2dfd1..b0f99533a2 100644 --- a/src/southbridge/amd/sb600/sb600_sm.c +++ b/src/southbridge/amd/sb600/sb600_sm.c @@ -36,8 +36,8 @@ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -#ifndef MAINBOARD_POWER_ON_AFTER_POWER_FAIL -#define MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif struct ioapicreg { @@ -164,7 +164,7 @@ static void sm_init(device_t dev) pm_iowrite(0x53, byte); /* power after power fail */ - on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; get_option(&on, "power_on_after_fail"); byte = pm_ioread(0x74); byte &= ~0x03; -- cgit v1.2.3