From 1bcd7fcb6199528fc82685e161d6b39f273a1962 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 28 Jul 2016 21:20:04 +0200 Subject: src/southbridge: Capitalize CPU, RAM and ROM Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Tobias Diedrich --- src/southbridge/amd/sb800/lpc.c | 2 +- src/southbridge/amd/sb800/sm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/amd/sb800') diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 18d4471545..3ba47a077b 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -59,7 +59,7 @@ static void lpc_init(device_t dev) interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); - /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */ + /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; diff --git a/src/southbridge/amd/sb800/sm.c b/src/southbridge/amd/sb800/sm.c index 8488d71b28..ba9e806a1f 100644 --- a/src/southbridge/amd/sb800/sm.c +++ b/src/southbridge/amd/sb800/sm.c @@ -83,7 +83,7 @@ static void sm_init(device_t dev) printk(BIOS_INFO, "sm_init().\n"); /* Don't rename APIC ID */ - /* TODO: We should call setup_ioapic() here. But kernel hangs if cpu is K8. + /* TODO: We should call setup_ioapic() here. But kernel hangs if CPU is K8. * We need to check out why and change back. */ clear_ioapic(VIO_APIC_VADDR); //setup_ioapic(IO_APIC_ADDR, 0); -- cgit v1.2.3