From ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 31 Aug 2016 19:22:16 +0200 Subject: src/southbridge: Code formating Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/southbridge/amd/sb700/Kconfig | 10 ---------- src/southbridge/amd/sb700/bootblock.c | 34 ---------------------------------- src/southbridge/amd/sb700/hda.c | 4 ++-- src/southbridge/amd/sb700/reset.c | 2 +- src/southbridge/amd/sb700/sm.c | 24 ++++++++++++------------ 5 files changed, 15 insertions(+), 59 deletions(-) (limited to 'src/southbridge/amd/sb700') diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 353c2a46c7..9a988a90f8 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS -config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI - bool "Enable high speed SPI clock" - default n - help - When set, the SPI clock will run at 33MHz instead - of the compatibility mode 16.5MHz. Note that not - all ROMs are capable of 33MHz operation, so you - will need to verify this option is appropriate for - the ROM you are using. - # Set for southbridge SP5100 which also uses SB700 driver config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c index dfa4102953..97e749ce08 100644 --- a/src/southbridge/amd/sb700/bootblock.c +++ b/src/southbridge/amd/sb700/bootblock.c @@ -20,10 +20,6 @@ #define IO_MEM_PORT_DECODE_ENABLE_5 0x48 #define IO_MEM_PORT_DECODE_ENABLE_6 0x4a -#define SPI_BASE_ADDRESS 0xa0 - -#define SPI_CONTROL_1 0xc -#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000 /* * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. @@ -96,37 +92,7 @@ static void sb700_enable_rom(void) pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8); } -static void sb700_configure_rom(void) -{ - pci_devfn_t dev; - uint32_t dword; - - dev = PCI_DEV(0, 0x14, 3); - - if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) { - uint32_t prev_spi_cfg; - volatile uint32_t *spi_mmio; - - /* Temporarily set up SPI access to change SPI speed */ - prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS); - dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */ - dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5); - dword |= (0x1 << 1); /* SpiRomEnable = 1 */ - pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword); - - spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1); - dword = *spi_mmio; - dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */ - dword |= (0x1 << 12); - *spi_mmio = dword; - - /* Restore previous SPI access */ - pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg); - } -} - static void bootblock_southbridge_init(void) { sb700_enable_rom(); - sb700_configure_rom(); } diff --git a/src/southbridge/amd/sb700/hda.c b/src/southbridge/amd/sb700/hda.c index c87ab6aa4f..8497cc5da2 100644 --- a/src/southbridge/amd/sb700/hda.c +++ b/src/southbridge/amd/sb700/hda.c @@ -97,7 +97,7 @@ static int wait_for_ready(void *base) int timeout = 50; - while(timeout--) { + while (timeout--) { u32 dword=read32(base + HDA_ICII_REG); if (!(dword & HDA_ICII_BUSY)) return 0; @@ -118,7 +118,7 @@ static int wait_for_valid(void *base) * same duration */ int timeout = 50; - while(timeout--) { + while (timeout--) { u32 dword = read32(base + HDA_ICII_REG); if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index 98429f315e..d0cd4a42f0 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -36,7 +36,7 @@ static void set_bios_reset(void) int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { dev = NODE_PCI(i, 0); htic = pci_read_config32(dev, HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 6d93b172f1..77ec722aa8 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -213,7 +213,7 @@ static void sm_init(device_t dev) } /*rpr v2.13 2.22 SMBUS PCI Config */ - byte = pci_read_config8(dev, 0xE1); + byte = pci_read_config8(dev, 0xE1); if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) { byte |= 1 << 0; } @@ -222,7 +222,7 @@ static void sm_init(device_t dev) */ //byte |= 1 << 2 | 1 << 3 | 1 << 4; byte |= 1 << 3 | 1 << 4; - pci_write_config8(dev, 0xE1, byte); + pci_write_config8(dev, 0xE1, byte); /* 2.5 Enabling Non-Posted Memory Write */ axindxc_reg(0x10, 1 << 9, 1 << 9); @@ -278,7 +278,7 @@ static void sm_init(device_t dev) u16 word; /* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */ - axindxc_reg(0x02, 1 << 9, 1 << 9); + axindxc_reg(0x02, 1 << 9, 1 << 9); abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0); abcfg_reg(0x1009C, 0x00000030, 0x00000030); abcfg_reg(0x10090, 0x00001E00, 0x00001E00); @@ -287,19 +287,19 @@ static void sm_init(device_t dev) abcfg_reg(0x58, 0x0000F800, 0x0000E800); /* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */ - axindxc_reg(0x02, 1 << 10, 1 << 10); + axindxc_reg(0x02, 1 << 10, 1 << 10); /* rpr v2.13 2.38 Unconditional Shutdown */ - byte = pci_read_config8(dev, 0x43); + byte = pci_read_config8(dev, 0x43); byte &= ~(1 << 3); - pci_write_config8(dev, 0x43, byte); + pci_write_config8(dev, 0x43, byte); word = pci_read_config16(dev, 0x38); word |= 1 << 12; - pci_write_config16(dev, 0x38, word); + pci_write_config16(dev, 0x38, word); byte |= 1 << 3; - pci_write_config8(dev, 0x43, byte); + pci_write_config8(dev, 0x43, byte); /* Enable southbridge MMIO decode */ dword = pci_read_config32(dev, SB_MMIO_CFG_REG); @@ -308,12 +308,12 @@ static void sm_init(device_t dev) dword |= 0x1; pci_write_config32(dev, SB_MMIO_CFG_REG, dword); } - byte = pci_read_config8(dev, 0xAE); - if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) - byte |= 1 << 4; + byte = pci_read_config8(dev, 0xAE); + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID)) + byte |= 1 << 4; byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */ byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */ - pci_write_config8(dev, 0xAE, byte); + pci_write_config8(dev, 0xAE, byte); /* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */ /* 4.12: Enabling AB and BIF Clock Gating */ -- cgit v1.2.3