From 3f9a62e5ade9bf2461c93ac8c6b52c4bdca09742 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 20 Jun 2013 20:25:21 +0300 Subject: Add pci_devfn_t and use with __SIMPLE_DEVICE__ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Declare the functions that may be used in both romstage and ramstage with simple device model. This will later allow to define PCI access functions for ramstage using the inlined functions from romstage. Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/3508 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/southbridge/amd/sb700/enable_usbdebug.c | 2 +- src/southbridge/amd/sb700/reset.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/southbridge/amd/sb700') diff --git a/src/southbridge/amd/sb700/enable_usbdebug.c b/src/southbridge/amd/sb700/enable_usbdebug.c index f0efe412ea..00eb4d924b 100644 --- a/src/southbridge/amd/sb700/enable_usbdebug.c +++ b/src/southbridge/amd/sb700/enable_usbdebug.c @@ -49,7 +49,7 @@ void set_debug_port(unsigned int port) */ void enable_usbdebug(unsigned int port) { - device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ + pci_devfn_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); diff --git a/src/southbridge/amd/sb700/reset.c b/src/southbridge/amd/sb700/reset.c index e457368370..ae79c4a440 100644 --- a/src/southbridge/amd/sb700/reset.c +++ b/src/southbridge/amd/sb700/reset.c @@ -36,7 +36,7 @@ static void set_bios_reset(void) { u32 nodes; u32 htic; - device_t dev; + pci_devfn_t dev; int i; nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; -- cgit v1.2.3