From 00c8c4a31632150fa711493f39e727da950ebe9f Mon Sep 17 00:00:00 2001 From: efdesign98 Date: Wed, 20 Jul 2011 12:37:58 -0600 Subject: Update AMD SR5650 and SB700 This updates the code for the AMD SR5650 and SB700 southbridges. Among other things, it changes the romstage.c files by replacing a .C file include with a pair of .H file includes. The .C file is now added to the romstage in the SB700 or SR5650 Makefile.inc. file to the romstage and ramstage elements. This particular change affects all mainboards that use the SB700, and their changes are include herein. These mainboards are: Advansus a785e, AMD Mahogany, Mahogany-fam10, Tilapia-fam10, Asrock 939a785gmh, Asus m4a78-em, m4a785-m, Gigabyte ma785gm, Iei Kino-780am2-fam10 Jetway pa78vm5 Supermicro h8scm_fam10 The nuvoton/wpcm450 earlysetup interface is changed because the file is no longer included in the mainboard romstage.c files. Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33 Signed-off-by: Frank Vibrans Signed-off-by: efdesign98 Reviewed-on: http://review.coreboot.org/107 Tested-by: build bot (Jenkins) Reviewed-by: Kerry She Reviewed-by: Marc Jones --- src/southbridge/amd/sb700/sm.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) mode change 100644 => 100755 src/southbridge/amd/sb700/sm.c (limited to 'src/southbridge/amd/sb700/sm.c') diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c old mode 100644 new mode 100755 index 7d341df327..05065b6dbe --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -30,7 +30,7 @@ #include #include #include "sb700.h" -#include "smbus.c" +#include "smbus.h" #define NMI_OFF 0 @@ -95,6 +95,20 @@ static void sm_init(device_t dev) byte |= 4 << 2; /* set NumSerIrqBits=4 */ pci_write_config8(dev, 0x69, byte); + /* Sx State Settings + * Note: These 2 registers need to be set correctly for the S-state + * to work properly. Otherwise the system may hang during resume + * from the S-state. + */ + /*Use 8us clock for delays in the S-state resume timing sequence.*/ + byte = pm_ioread(0x65); + byte &= ~(1 << 7); + pm_iowrite(0x65, byte); + /* Delay the APIC interrupt to the CPU until the system has fully resumed from the S-state. */ + byte = pm_ioread(0x68); + byte |= 1 << 2; + pm_iowrite(0x68, byte); + /* IRQ0From8254 */ byte = pci_read_config8(dev, 0x41); byte &= ~(1 << 7); @@ -219,10 +233,10 @@ static void sm_init(device_t dev) * Transactions for the K8 Platform (for All Revisions) */ abcfg_reg(0x10090, 1 << 8, 1 << 8); - /* ACPI_SOFT_CLOCK_THROTTLE_PERIOD */ + /* Set ACPI Software clock Throttling Period to 244 us*/ byte = pm_ioread(0x68); byte &= ~(3 << 6); - byte |= (2 << 6); /* 224us */ + byte |= (2 << 6); /* 244us */ pm_iowrite(0x68, byte); if (REV_SB700_A15 == rev) { @@ -367,16 +381,16 @@ static void sb700_sm_read_resources(device_t dev) res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; - /* Linux ACPI crashes when it is 1. For late debugging. */ + /* HPET */ res = new_resource(dev, 0xB4); /* TODO: test hpet */ res->base = 0xfed00000; /* reset hpet to widely accepted address */ res->size = 0x400; res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; /* dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; */ @@ -387,7 +401,7 @@ static void sb700_sm_read_resources(device_t dev) res->limit = 0xFFFFUL; /* res->base + res->size -1; */ res->align = 8; res->gran = 8; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; compact_resources(dev); } -- cgit v1.2.3