From c3422235b14d97c16bd13113c522827d1cfda9b4 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Mon, 28 Mar 2011 03:33:10 +0000 Subject: SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx. Since the SB700 has changed to sb7xx_51xx, change legacy name in other mainboard. Signed-off-by: Zheng Bao Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/sb700/sata.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/southbridge/amd/sb700/sata.c') diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 1ad9bdd9df..4838d93658 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -54,7 +54,7 @@ static int sata_drive_detect(int portnum, u16 iobar) } /* This function can be overloaded in mainboard.c */ -void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) +void __attribute__((weak)) sb7xx_51xx_setup_sata_phys(struct device *dev) { /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ pci_write_config16(dev, 0x86, 0x2c00); @@ -184,12 +184,17 @@ static void sata_init(struct device *dev) /* Program the watchdog counter to 0x10 */ byte = 0x10; pci_write_config8(dev, 0x46, byte); - sb700_setup_sata_phys(dev); + sb7xx_51xx_setup_sata_phys(dev); /* Enable the I/O, MM, BusMaster access for SATA */ byte = pci_read_config8(dev, 0x4); byte |= 7 << 0; pci_write_config8(dev, 0x4, byte); +#ifdef CONFIG_SOUTHBRIDGE_AMD_SP5100 + /* Master Latency Timer */ + pci_write_config32(dev, 0xC, 0x00004000); +#endif + /* RPR7.7 SATA drive detection. */ /* Use BAR5+0x128,BAR0 for Primary Slave */ /* Use BAR5+0x1A8,BAR0 for Primary Slave */ -- cgit v1.2.3