From ee3ec8e21256e544ef0a32f283a65c0c47040948 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Fri, 23 Oct 2015 22:28:26 -0500 Subject: southbridge/amd/sb700: Set up uninitialized devices in early boot LPC decodes were not enabled, leading to a failure of POST 80 cards and similar debugging devices. Enable the relevant LPC decodes to allow debugging. Additionally, the SMBUS controllers were not properly set up. Enable both the primary and auxiliary controllers. Finally, K10 and higher CPUs were hanging during boot due to a misconfigued IOAPIC. Properly configure the IOAPIC. Change-Id: I9ffb6542ce445ac971fb81f4f554e7f1313e6a98 Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/12177 Reviewed-by: Peter Stuge Tested-by: build bot (Jenkins) --- src/southbridge/amd/sb700/lpc.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/southbridge/amd/sb700/lpc.c') diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a39ec1849e..0cc1e8bd3c 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson , Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -45,6 +46,8 @@ static void lpc_init(device_t dev) u32 dword; device_t sm_dev; + printk(BIOS_SPEW, "%s\n", __func__); + /* Enable the LPC Controller */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_read_config32(sm_dev, 0x64); -- cgit v1.2.3