From ba28e8d73b143def8dfe7c0dc7cfcbce83c601a1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 31 Aug 2016 19:22:16 +0200 Subject: src/southbridge: Code formating Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16291 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/southbridge/amd/sb700/Kconfig | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/southbridge/amd/sb700/Kconfig') diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 353c2a46c7..9a988a90f8 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_HARD_RESET select SMBUS_HAS_AUX_CHANNELS -config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI - bool "Enable high speed SPI clock" - default n - help - When set, the SPI clock will run at 33MHz instead - of the compatibility mode 16.5MHz. Note that not - all ROMs are capable of 33MHz operation, so you - will need to verify this option is appropriate for - the ROM you are using. - # Set for southbridge SP5100 which also uses SB700 driver config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 bool -- cgit v1.2.3