From 24284270c73ba4e35af10ea9054f084c989dff52 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 17:23:12 +0100 Subject: sb/amd/sb700: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: Iffa4f54b2d1b43b6710447e69061c6ed433bff1d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36967 Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/southbridge/amd/sb700/Kconfig | 68 --------------------------------------- 1 file changed, 68 deletions(-) delete mode 100644 src/southbridge/amd/sb700/Kconfig (limited to 'src/southbridge/amd/sb700/Kconfig') diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig deleted file mode 100644 index 58dc75a5de..0000000000 --- a/src/southbridge/amd/sb700/Kconfig +++ /dev/null @@ -1,68 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOUTHBRIDGE_AMD_SB700 - bool - -if SOUTHBRIDGE_AMD_SB700 - -config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy - def_bool y - select IOAPIC - select HAVE_USBDEBUG_OPTIONS - select SMBUS_HAS_AUX_CHANNELS - select HAVE_POWER_STATE_AFTER_FAILURE - select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE - -config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI - bool "Enable high speed SPI clock" - default n - help - When set, the SPI clock will run at 33MHz instead - of the compatibility mode 16.5MHz. Note that not - all ROMs are capable of 33MHz operation, so you - will need to verify this option is appropriate for - the ROM you are using. - -# Set for southbridge SP5100 which also uses SB700 driver -config SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - bool - default n - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/sb700/bootblock.c" - -config SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT - bool - default n - -config SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA - bool - default n - -config SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD - hex - default 0xf - -config EHCI_BAR - hex - default 0xfef00000 - -config HPET_MIN_TICKS - hex - default 0x14 - -endif # SOUTHBRIDGE_AMD_SB700 -- cgit v1.2.3