From c02b4fc9db3c3c1e263027382697b566127f66bb Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 22 Mar 2010 11:42:32 +0000 Subject: printk_foo -> printk(BIOS_FOO, ...) Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/southbridge/amd/rs780/rs780.c | 24 ++++++------ src/southbridge/amd/rs780/rs780_cmn.c | 10 ++--- src/southbridge/amd/rs780/rs780_early_setup.c | 42 ++++++++++----------- src/southbridge/amd/rs780/rs780_gfx.c | 54 +++++++++++++-------------- src/southbridge/amd/rs780/rs780_ht.c | 2 +- src/southbridge/amd/rs780/rs780_pcie.c | 10 ++--- 6 files changed, 71 insertions(+), 71 deletions(-) (limited to 'src/southbridge/amd/rs780') diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index b7ec1154ce..471603f865 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -120,9 +120,9 @@ void rs780_nb_pci_table(device_t nb_dev) /* Program NB PCI table. */ temp16 = pci_read_config16(nb_dev, 0x04); - printk_debug("NB_PCI_REG04 = %x.\n", temp16); + printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16); temp32 = pci_read_config32(nb_dev, 0x84); - printk_debug("NB_PCI_REG84 = %x.\n", temp32); + printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32); pci_write_config8(nb_dev, 0x4c, 0x42); @@ -131,7 +131,7 @@ void rs780_nb_pci_table(device_t nb_dev) pci_write_config8(nb_dev, 0x4e, temp8); temp32 = pci_read_config32(nb_dev, 0x4c); - printk_debug("NB_PCI_REG4C = %x.\n", temp32); + printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); /* disable GFX debug. */ temp8 = pci_read_config8(nb_dev, 0x8d); @@ -250,7 +250,7 @@ void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) /* Enable PCIe configuration space. */ set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28); - printk_info("GC is accessible from now on.\n"); + printk(BIOS_INFO, "GC is accessible from now on.\n"); } /*********************************************** @@ -272,7 +272,7 @@ void rs780_enable(device_t dev) device_t nb_dev = 0, sb_dev = 0; int dev_ind; - printk_info("rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); + printk(BIOS_INFO, "rs780_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev)); nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!nb_dev) { @@ -290,7 +290,7 @@ void rs780_enable(device_t dev) dev_ind = dev->path.pci.devfn >> 3; switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ - printk_info("Bus-0, Dev-0, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ config_gpp_core(nb_dev, sb_dev); rs780_gpp_sb_init(nb_dev, sb_dev, 8); @@ -304,12 +304,12 @@ void rs780_enable(device_t dev) break; case 1: /* bus0, dev1, APC. */ - printk_info("Bus-0, Dev-1, Fun-0.\n"); + printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n"); rs780_nb_gfx_dev_table(nb_dev, dev); break; case 2: /* bus0, dev2,3, two GFX */ case 3: - printk_info("Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); if (dev->enabled) @@ -319,7 +319,7 @@ void rs780_enable(device_t dev) case 5: case 6: case 7: - printk_info("Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", + printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind, (dev->enabled ? 0 : 1) << dev_ind); @@ -327,7 +327,7 @@ void rs780_enable(device_t dev) rs780_gpp_sb_init(nb_dev, dev, dev_ind); break; case 8: /* bus0, dev8, SB */ - printk_info("Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); + printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled); set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6, (dev->enabled ? 1 : 0) << 6); if (dev->enabled) @@ -336,7 +336,7 @@ void rs780_enable(device_t dev) break; case 9: /* bus 0, dev 9,10, GPP */ case 10: - printk_info("Bus-0, Dev-9, 10, Fun-0. enable=%d\n", + printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", dev->enabled); enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), @@ -346,7 +346,7 @@ void rs780_enable(device_t dev) /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ break; default: - printk_debug("unknown dev: %s\n", dev_path(dev)); + printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); } } diff --git a/src/southbridge/amd/rs780/rs780_cmn.c b/src/southbridge/amd/rs780/rs780_cmn.c index bf27794fc7..ab91074ad2 100644 --- a/src/southbridge/amd/rs780/rs780_cmn.c +++ b/src/southbridge/amd/rs780/rs780_cmn.c @@ -48,7 +48,7 @@ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - printk_debug("addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg; @@ -61,7 +61,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask /*get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; - /*printk_debug("write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, + /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ addr |= dev->bus->secondary << 20 | /* bus num */ dev->path.pci.devfn << 12 | reg_pos; @@ -271,7 +271,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) mdelay(40); udelay(200); lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */ - printk_debug("PcieLinkTraining port=%x:lc current state=%x\n", + printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n", port, lc_state); current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */ @@ -297,7 +297,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg |= lane_mask << 8 | lane_mask; reg = 0xE0E0; /* TODO: See the comments in rs780_pcie.c, at about line 145. */ nbpcie_ind_write_index(nb_dev, 0x65 | gfx_gpp_sb_sel, reg); - printk_debug("link_width=%x, lane_mask=%x", + printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x", current_link_width, lane_mask); set_pcie_reset(); mdelay(1); @@ -311,7 +311,7 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); - printk_debug("PcieTrainPort reg=0x%x\n", reg); + printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ diff --git a/src/southbridge/amd/rs780/rs780_early_setup.c b/src/southbridge/amd/rs780/rs780_early_setup.c index 5b9616f3ca..159d51f52e 100644 --- a/src/southbridge/amd/rs780/rs780_early_setup.c +++ b/src/southbridge/amd/rs780/rs780_early_setup.c @@ -147,25 +147,25 @@ static void get_cpu_rev() u32 eax; eax = cpuid_eax(1); - printk_info("get_cpu_rev EAX=0x%x.\n", eax); + printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax); if (eax <= 0xfff) - printk_info("CPU Rev is K8_Cx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Cx.\n"); else if (eax <= 0x10fff) - printk_info("CPU Rev is K8_Dx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Dx.\n"); else if (eax <= 0x20fff) - printk_info("CPU Rev is K8_Ex.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Ex.\n"); else if (eax <= 0x40fff) - printk_info("CPU Rev is K8_Fx.\n"); + printk(BIOS_INFO, "CPU Rev is K8_Fx.\n"); else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */ - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else if (eax <= 0X60FF0) - printk_info("CPU Rev is K8_G0.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G0.\n"); else if (eax <= 0x100000) - printk_info("CPU Rev is K8_G1.\n"); + printk(BIOS_INFO, "CPU Rev is K8_G1.\n"); else if (eax <= 0x100f00) - printk_info("CPU Rev is Fam 10.\n"); + printk(BIOS_INFO, "CPU Rev is Fam 10.\n"); else - printk_info("CPU Rev is K8_10.\n"); + printk(BIOS_INFO, "CPU Rev is K8_10.\n"); } static u8 is_famly10() @@ -246,7 +246,7 @@ static void rs780_htinit() ************************/ reg = pci_read_config32(cpu_f0, 0x88); cpu_ht_freq = (reg & 0xf00) >> 8; - printk_info("rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); + printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq); rs780_f0 = PCI_DEV(0, 0, 0); //set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28); @@ -260,7 +260,7 @@ static void rs780_htinit() * So we check 6 only, it would be faster. */ if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) || (cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) { - printk_info("rs780_htinit: HT1 mode\n"); + printk(BIOS_INFO, "rs780_htinit: HT1 mode\n"); /* HT1 mode, RPR 8.4.2 */ /* set IBIAS code */ @@ -268,7 +268,7 @@ static void rs780_htinit() /* Optimizes chipset HT transmitter drive strength */ set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1); } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { - printk_info("rs780_htinit: HT3 mode\n"); + printk(BIOS_INFO, "rs780_htinit: HT3 mode\n"); #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ /* HT3 mode, RPR 8.4.3 */ @@ -330,7 +330,7 @@ static void k8_optimization() device_t k8_f0, k8_f2, k8_f3; msr_t msr; - printk_info("k8_optimization()\n"); + printk(BIOS_INFO, "k8_optimization()\n"); k8_f0 = PCI_DEV(0, 0x18, 0); k8_f2 = PCI_DEV(0, 0x18, 2); k8_f3 = PCI_DEV(0, 0x18, 3); @@ -373,7 +373,7 @@ void fam10_optimization() msr_t msr; u32 val; - printk_info("fam10_optimization()\n"); + printk(BIOS_INFO, "fam10_optimization()\n"); cpu_f0 = PCI_DEV(0, 0x18, 0); cpu_f2 = PCI_DEV(0, 0x18, 2); @@ -612,7 +612,7 @@ static void rs780_por_htiu_index_init(device_t nb_dev) *****************************************/ static void rs780_por_init(device_t nb_dev) { - printk_info("rs780_por_init\n"); + printk(BIOS_INFO, "rs780_por_init\n"); /* ATINB_PCICFG_POR_TABLE, initialize the values for rs780 PCI Config registers */ rs780_por_pcicfg_init(nb_dev); @@ -642,20 +642,20 @@ static void rs780_before_pci_init() static void rs780_early_setup() { device_t nb_dev = PCI_DEV(0, 0, 0); - printk_info("rs780_early_setup()\n"); + printk(BIOS_INFO, "rs780_early_setup()\n"); get_cpu_rev(); - /* The printk_info(s) below cause the system unstable. */ + /* The printk(BIOS_INFO, s) below cause the system unstable. */ switch (get_nb_rev(nb_dev)) { case REV_RS780_A11: - /* printk_info("NB Revision is A11.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A11.\n"); */ break; case REV_RS780_A12: - /* printk_info("NB Revision is A12.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A12.\n"); */ break; case REV_RS780_A13: - /* printk_info("NB Revision is A13.\n"); */ + /* printk(BIOS_INFO, "NB Revision is A13.\n"); */ break; } diff --git a/src/southbridge/amd/rs780/rs780_gfx.c b/src/southbridge/amd/rs780/rs780_gfx.c index aa46451410..808bcb175f 100644 --- a/src/southbridge/amd/rs780/rs780_gfx.c +++ b/src/southbridge/amd/rs780/rs780_gfx.c @@ -55,7 +55,7 @@ static u32 clkind_read(device_t dev, u32 index) static void clkind_write(device_t dev, u32 index, u32 data) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; - /* printk_info("gfx bar 2 %02x\n", gfx_bar2); */ + /* printk(BIOS_INFO, "gfx bar 2 %02x\n", gfx_bar2); */ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index | 1<<7; *(u32*)(gfx_bar2+CLK_CNTL_DATA) = data; @@ -67,7 +67,7 @@ static void clkind_write(device_t dev, u32 index, u32 data) */ static void rs780_gfx_read_resources(device_t dev) { - printk_info("rs780_gfx_read_resources.\n"); + printk(BIOS_INFO, "rs780_gfx_read_resources.\n"); /* The initial value of 0x24 is 0xFFFFFFFF, which is confusing. Even if we write 0xFFFFFFFF into it, it will be 0xFFF00000, @@ -189,7 +189,7 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) { tempdev = dev_find_slot(Bus, Dev << 3); Value = pci_read_config32(tempdev, 0); - printk_debug("Dev ID %x \n", Value); + printk(BIOS_DEBUG, "Dev ID %x \n", Value); if((Value & 0xffff) == 0x1102) {//Creative //Found Creative SB @@ -220,7 +220,7 @@ CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) } } } - printk_debug(" MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit); + printk(BIOS_DEBUG, " MMIOStart %x MMIOLimit %x \n", MMIOStart, MMIOLimit); if (MMIOStart < MMIOLimit) { Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO); @@ -310,7 +310,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); - printk_info("internal_gfx_pci_dev_init device=%x, vendor=%x.\n", + printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", deviceid, vendorid); command = pci_read_config16(dev, 0x04); @@ -420,7 +420,7 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */ vgainfo.ulReserved1[0] = 0; vgainfo.ulReserved1[1] = 0; value = pci_read_config32(k8_f2, 0x94); - printk_debug("MEMCLK = %x\n", value&0x7); + printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7); vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */ vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */ vgainfo.ulMinSidePortClock = 0; /* disable SP. */ @@ -447,14 +447,14 @@ static void internal_gfx_pci_dev_init(struct device *dev) vgainfo.usBootUpNBVoltage = 0x1a; value = pci_read_config32(nb_dev, 0xd0); - printk_debug("NB HT speed = %x.\n", value); + printk(BIOS_DEBUG, "NB HT speed = %x.\n", value); value = pci_read_config32(k8_f0, 0x88); - printk_debug("CPU HT speed = %x.\n", value); + printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value); vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */ /* HT width. */ value = pci_read_config32(nb_dev, 0xc8); - printk_debug("HT width = %x.\n", value); + printk(BIOS_DEBUG, "HT width = %x.\n", value); vgainfo.usMinHTLinkWidth = 16; vgainfo.usMaxHTLinkWidth = 16; vgainfo.usUMASyncStartDelay = 322; @@ -585,10 +585,10 @@ static void rs780_internal_gfx_enable(device_t dev) u32 FB_Start, FB_End; #endif - printk_info("rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); + printk(BIOS_INFO, "rs780_internal_gfx_enable dev = 0x%p, nb_dev = 0x%p.\n", dev, nb_dev); sysmem = rdmsr(0xc001001a); - printk_info("sysmem = %x_%x\n", sysmem.hi, sysmem.lo); + printk(BIOS_INFO, "sysmem = %x_%x\n", sysmem.hi, sysmem.lo); /* The system top memory in 780. */ pci_write_config32(nb_dev, 0x90, sysmem.lo); @@ -826,12 +826,12 @@ static void single_port_configuration(device_t nb_dev, device_t dev) struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_info("rs780_gfx_init single_port_configuration.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration.\n"); /* step 12 training, releases hold training for GFX port 0 (device 2) */ PcieReleasePortTraining(nb_dev, dev, 2); result = PcieTrainPort(nb_dev, dev, 2); - printk_info("rs780_gfx_init single_port_configuration step12.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step12.\n"); /* step 13 Power Down Control */ /* step 13.1 Enables powering down transmitter and receiver pads along with PLL macros. */ @@ -851,7 +851,7 @@ static void single_port_configuration(device_t nb_dev, device_t dev) set_pcie_enable_bits(dev, 0xA2, 0xFF, 0x1); reg32 = nbpcie_p_read_index(dev, 0x29); width = reg32 & 0xFF; - printk_debug("GFX Inactive Lanes = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX Inactive Lanes = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -868,11 +868,11 @@ static void single_port_configuration(device_t nb_dev, device_t dev) break; } } - printk_info("rs780_gfx_init single_port_configuration step13.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step13.\n"); /* step 14 Reset Enumeration Timer, disables the shortening of the enumeration timer */ set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19); - printk_info("rs780_gfx_init single_port_configuration step14.\n"); + printk(BIOS_INFO, "rs780_gfx_init single_port_configuration step14.\n"); } static void dual_port_configuration(device_t nb_dev, device_t dev) @@ -905,7 +905,7 @@ static void dual_port_configuration(device_t nb_dev, device_t dev) } else { /* step 16.b Link Training was successful */ reg32 = nbpcie_p_read_index(dev, 0xa2); width = (reg32 >> 4) & 0x7; - printk_debug("GFX LC_LINK_WIDTH = 0x%x.\n", width); + printk(BIOS_DEBUG, "GFX LC_LINK_WIDTH = 0x%x.\n", width); switch (width) { case 1: case 2: @@ -983,7 +983,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_info("rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", + printk(BIOS_INFO, "rs780_gfx_init, nb_dev=0x%p, dev=0x%p, port=0x%x.\n", nb_dev, dev, port); /* GFX Core Initialization */ @@ -995,13 +995,13 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 3, 1 << 3); } - printk_info("rs780_gfx_init step1.\n"); + printk(BIOS_INFO, "rs780_gfx_init step1.\n"); /* step 1.1, dual-slot gfx configuration (only need if CMOS option is enabled) */ /* AMD calls the configuration CrossFire */ if (cfg->gfx_dual_slot) set_nbmisc_enable_bits(nb_dev, 0x0, 0xf << 8, 5 << 8); - printk_info("rs780_gfx_init step2.\n"); + printk(BIOS_INFO, "rs780_gfx_init step2.\n"); /* step 2, TMDS, (only need if CMOS option is enabled) */ if (cfg->gfx_tmds) { @@ -1020,7 +1020,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 1 << 6 | 1 << 8 | 1 << 10); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk_info("misc 28 = %x\n", reg32); + printk(BIOS_INFO, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 1 << 31); @@ -1038,7 +1038,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) set_nbmisc_enable_bits(nb_dev, 0x28, 3 << 6 | 3 << 8 | 3 << 10, 0); reg32 = nbmisc_read_index(nb_dev, 0x28); - printk_info("misc 28 = %x\n", reg32); + printk(BIOS_INFO, "misc 28 = %x\n", reg32); /* 5.9.1.6.Selects the single ended GFX REFCLK to be the source for core logic. */ set_nbmisc_enable_bits(nb_dev, 0x6C, 1 << 31, 0 << 31); @@ -1079,7 +1079,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* release hold training for device 2. GFX initialization is done. */ set_nbmisc_enable_bits(nb_dev, 0x8, 1 << 4, 0 << 4); dynamic_link_width_control(nb_dev, dev, cfg->gfx_link_width); - printk_info("rs780_gfx_init step7.\n"); + printk(BIOS_INFO, "rs780_gfx_init step7.\n"); return; } @@ -1087,11 +1087,11 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.1 sets RCB timeout to be 25ms */ /* 5.9.12.2. RCB Cpl timeout on link down. */ set_pcie_enable_bits(dev, 0x70, 7 << 16 | 1 << 19, 4 << 16 | 1 << 19); - printk_info("rs780_gfx_init step5.9.12.1.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.1.\n"); /* step 5.9.12.3 disables slave ordering logic */ set_pcie_enable_bits(nb_dev, 0x20, 1 << 8, 1 << 8); - printk_info("rs780_gfx_init step5.9.12.3.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.3.\n"); /* step 5.9.12.4 sets DMA payload size to 64 bytes */ set_pcie_enable_bits(nb_dev, 0x10, 7 << 10, 4 << 10); @@ -1113,7 +1113,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) /* 5.9.12.9 CMGOOD_OVERRIDE for end point initiated lane degradation. */ set_nbmisc_enable_bits(nb_dev, 0x6a, 1 << 17, 1 << 17); - printk_info("rs780_gfx_init step5.9.12.9.\n"); + printk(BIOS_INFO, "rs780_gfx_init step5.9.12.9.\n"); /* 5.9.12.10 Sets the timer in Config state from 20us to */ /* 5.9.12.11 De-asserts RX_EN in L0s. */ @@ -1188,7 +1188,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port) dual_port_configuration(nb_dev, dev); break; default: - printk_info("Incorrect configuration of external gfx slot.\n"); + printk(BIOS_INFO, "Incorrect configuration of external gfx slot.\n"); break; } } diff --git a/src/southbridge/amd/rs780/rs780_ht.c b/src/southbridge/amd/rs780/rs780_ht.c index b3fa05a529..03d4f84645 100644 --- a/src/southbridge/amd/rs780/rs780_ht.c +++ b/src/southbridge/amd/rs780/rs780_ht.c @@ -53,7 +53,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_info("pcie_init in rs780_ht.c\n"); + printk(BIOS_INFO, "pcie_init in rs780_ht.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); diff --git a/src/southbridge/amd/rs780/rs780_pcie.c b/src/southbridge/amd/rs780/rs780_pcie.c index b778af3aa6..186266b8f1 100644 --- a/src/southbridge/amd/rs780/rs780_pcie.c +++ b/src/southbridge/amd/rs780/rs780_pcie.c @@ -106,7 +106,7 @@ static void pcie_init(struct device *dev) /* Enable pci error detecting */ u32 dword; - printk_debug("pcie_init in rs780_pcie.c\n"); + printk(BIOS_DEBUG, "pcie_init in rs780_pcie.c\n"); /* System error enable */ dword = pci_read_config32(dev, 0x04); @@ -216,7 +216,7 @@ static void switching_gpp_configurations(device_t nb_dev, device_t sb_dev) *****************************************************************/ void enable_pcie_bar3(device_t nb_dev) { - printk_debug("enable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "enable_pcie_bar3()\n"); set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */ set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16); @@ -232,7 +232,7 @@ void enable_pcie_bar3(device_t nb_dev) *****************************************************************/ void disable_pcie_bar3(device_t nb_dev) { - printk_debug("disable_pcie_bar3()\n"); + printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); @@ -255,7 +255,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) u32 gfx_gpp_sb_sel; struct southbridge_amd_rs780_config *cfg = (struct southbridge_amd_rs780_config *)nb_dev->chip_info; - printk_debug("gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port); + printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%p\n", nb_dev, dev, port); gfx_gpp_sb_sel = port >= 4 && port <= 8 ? PCIE_CORE_INDEX_GPPSB : /* 4,5,6,7,8 */ @@ -369,7 +369,7 @@ void rs780_gpp_sb_init(device_t nb_dev, device_t dev, u32 port) PcieReleasePortTraining(nb_dev, dev, port); if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) { u8 res = PcieTrainPort(nb_dev, dev, port); - printk_debug("PcieTrainPort port=0x%x result=%d\n", port, res); + printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res); if (res) { AtiPcieCfg.PortDetect |= 1 << port; } -- cgit v1.2.3