From 400ce55566caa541304b2483e61bcc2df941998c Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 12 Oct 2018 10:54:30 +0200 Subject: cpu/amd: Use common AMD's MSR Phase 1. Due to the size of the effort, this CL is broken into several phases. Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/29065 Tested-by: build bot (Jenkins) Reviewed-by: Richard Spiegel --- src/southbridge/amd/rs780/early_setup.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/southbridge/amd/rs780') diff --git a/src/southbridge/amd/rs780/early_setup.c b/src/southbridge/amd/rs780/early_setup.c index ab75e5f57f..865b577279 100644 --- a/src/southbridge/amd/rs780/early_setup.c +++ b/src/southbridge/amd/rs780/early_setup.c @@ -18,6 +18,7 @@ #include #include #include +#include #include "rev.h" #include "rs780.h" @@ -317,10 +318,10 @@ static void k8_optimization(void) set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2); set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); - msr = rdmsr(0xC001001F); + msr = rdmsr(NB_CFG_MSR); msr.lo &= ~(1 << 9); msr.hi &= ~(1 << 4); - wrmsr(0xC001001F, msr); + wrmsr(NB_CFG_MSR, msr); } #else #define k8_optimization() do {} while (0) -- cgit v1.2.3