From 00ad8dfa181e627cbf566c575d1b95ffc7e435af Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 23 Jan 2019 15:56:30 +0200 Subject: device/pci_ops: Drop unused parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the bus parameter, we do not use it. It would still be possible to do per-bus selection by evaluating the bus number, but currently we do not have need for that either. Change-Id: I09e928b4677d9db2eee12730ba7b3fdd8837805c Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/31678 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Felix Held --- src/southbridge/amd/rs780/rs780.c | 41 +++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 21 deletions(-) (limited to 'src/southbridge/amd/rs780/rs780.c') diff --git a/src/southbridge/amd/rs780/rs780.c b/src/southbridge/amd/rs780/rs780.c index c5e38c130c..28e337f5d0 100644 --- a/src/southbridge/amd/rs780/rs780.c +++ b/src/southbridge/amd/rs780/rs780.c @@ -31,33 +31,32 @@ void static rs780_config_misc_clk(struct device *nb_dev) u32 reg; u16 word; u8 byte; - struct bus pbus; /* fake bus for dev0 fun1 */ reg = pci_read_config32(nb_dev, 0x4c); reg |= 1 << 0; pci_write_config32(nb_dev, 0x4c, reg); - word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xf8); + word = pci_cf8_conf1.read16(0, 1, 0xf8); word &= 0xf00; - pci_cf8_conf1.write16(&pbus, 0, 1, 0xf8, word); + pci_cf8_conf1.write16(0, 1, 0xf8, word); - word = pci_cf8_conf1.read16(&pbus, 0, 1, 0xe8); + word = pci_cf8_conf1.read16(0, 1, 0xe8); word &= ~((1 << 12) | (1 << 13) | (1 << 14)); word |= 1 << 13; - pci_cf8_conf1.write16(&pbus, 0, 1, 0xe8, word); + pci_cf8_conf1.write16(0, 1, 0xe8, word); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x94); + reg = pci_cf8_conf1.read32(0, 1, 0x94); reg &= ~((1 << 16) | (1 << 24) | (1 << 28)); - pci_cf8_conf1.write32(&pbus, 0, 1, 0x94, reg); + pci_cf8_conf1.write32(0, 1, 0x94, reg); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); + reg = pci_cf8_conf1.read32(0, 1, 0x8c); reg &= ~((1 << 13) | (1 << 14) | (1 << 24) | (1 << 25)); reg |= 1 << 13; - pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); + pci_cf8_conf1.write32(0, 1, 0x8c, reg); - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_cf8_conf1.read32(0, 1, 0xcc); reg |= 1 << 24; - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_cf8_conf1.write32(0, 1, 0xcc, reg); reg = nbmc_read_index(nb_dev, 0x7a); reg &= ~0x3f; @@ -66,31 +65,31 @@ void static rs780_config_misc_clk(struct device *nb_dev) set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11); nbmc_write_index(nb_dev, 0x7a, reg); /* Powering Down efuse and strap block clocks after boot-up. GFX Mode. */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_cf8_conf1.read32(0, 1, 0xcc); reg &= ~(1 << 23); reg |= 1 << 24; - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_cf8_conf1.write32(0, 1, 0xcc, reg); /* Programming NB CLK table. */ - byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe0); + byte = pci_cf8_conf1.read8(0, 1, 0xe0); byte |= 0x01; - pci_cf8_conf1.write8(&pbus, 0, 1, 0xe0, byte); + pci_cf8_conf1.write8(0, 1, 0xe0, byte); #if 0 /* Powerdown reference clock to graphics core PLL in northbridge only mode */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0x8c); + reg = pci_cf8_conf1.read32(0, 1, 0x8c); reg |= 1 << 21; - pci_cf8_conf1.write32(&pbus, 0, 1, 0x8c, reg); + pci_cf8_conf1.write32(0, 1, 0x8c, reg); /* Powering Down efuse and strap block clocks after boot-up. NB Only Mode. */ - reg = pci_cf8_conf1.read32(&pbus, 0, 1, 0xcc); + reg = pci_cf8_conf1.read32(0, 1, 0xcc); reg |= (1 << 23) | (1 << 24); - pci_cf8_conf1.write32(&pbus, 0, 1, 0xcc, reg); + pci_cf8_conf1.write32(0, 1, 0xcc, reg); /* Powerdown clock to memory controller in northbridge only mode */ - byte = pci_cf8_conf1.read8(&pbus, 0, 1, 0xe4); + byte = pci_cf8_conf1.read8(0, 1, 0xe4); byte |= 1 << 0; - pci_cf8_conf1.write8(&pbus, 0, 1, 0xe4, reg); + pci_cf8_conf1.write8(0, 1, 0xe4, reg); /* CLKCFG:0xE8 Bit[17] = 0x1 Powerdown clock to IOC GFX block in no external graphics mode */ /* TODO: */ -- cgit v1.2.3