From 1bcd7fcb6199528fc82685e161d6b39f273a1962 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 28 Jul 2016 21:20:04 +0200 Subject: src/southbridge: Capitalize CPU, RAM and ROM Change-Id: I01413b9f8b77ecdcb781340f04c2fe9e24810264 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15941 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Tobias Diedrich --- src/southbridge/amd/pi/hudson/lpc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/southbridge/amd/pi') diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 057058bc8b..9f01020f11 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -63,7 +63,7 @@ static void lpc_init(device_t dev) interrupt and visit LPC. */ pci_write_config8(dev, 0x78, byte); - /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */ + /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ byte = pci_read_config8(dev, 0xBB); byte |= 1 << 0 | 1 << 3; -- cgit v1.2.3