From 520717dff196e1d1ed61f72a8abadbc114ee6ba1 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Sun, 15 Dec 2019 21:37:48 +0200
Subject: AGESA,binaryPI: Drop remains of ROMCC_BOOTBLOCK
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Change-Id: I507ac6d483d9854852d6d01f10544c450b8d33cc
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37440
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/southbridge/amd/pi/hudson/Kconfig      |  4 ----
 src/southbridge/amd/pi/hudson/Makefile.inc |  2 --
 src/southbridge/amd/pi/hudson/bootblock.c  | 19 +++++--------------
 3 files changed, 5 insertions(+), 20 deletions(-)

(limited to 'src/southbridge/amd/pi/hudson')

diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index 01f3937321..ea37e3ee12 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -34,10 +34,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select SOC_AMD_COMMON_BLOCK
 	select SOC_AMD_COMMON_BLOCK_ACPIMMIO
 
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/pi/hudson/bootblock.c"
-
 config EHCI_BAR
 	hex
 	default 0xfef00000
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 4aa9babafe..9d985e6d7b 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -28,11 +28,9 @@
 #
 #*****************************************************************************
 
-ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y)
 bootblock-y += bootblock.c
 bootblock-y += early_setup.c
 bootblock-$(CONFIG_USBDEBUG) += enable_usbdebug.c
-endif
 
 romstage-y += early_setup.c
 romstage-y += enable_usbdebug.c
diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c
index d16aecc2a8..77a4570830 100644
--- a/src/southbridge/amd/pi/hudson/bootblock.c
+++ b/src/southbridge/amd/pi/hudson/bootblock.c
@@ -14,7 +14,10 @@
  */
 
 #include <stdint.h>
+#include <arch/bootblock.h>
+#include <amdblocks/acpimmio.h>
 #include <device/pci_ops.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@@ -56,23 +59,12 @@ static void hudson_enable_rom(void)
 	pci_io_write_config16(dev, 0x6e, 0xffff);
 }
 
-static void bootblock_southbridge_init(void)
-{
-	hudson_enable_rom();
-}
-
-#if !CONFIG(ROMCC_BOOTBLOCK)
-
-#include <bootblock_common.h>
-#include <amdblocks/acpimmio.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
-
-void bootblock_soc_early_init(void)
+void bootblock_early_southbridge_init(void)
 {
 	pci_devfn_t dev;
 	u32 data;
 
-	bootblock_southbridge_init();
+	hudson_enable_rom();
 	if (CONFIG(SOUTHBRIDGE_AMD_PI_BOLTON))
 		enable_acpimmio_decode_pm24();
 	else
@@ -111,4 +103,3 @@ void bootblock_soc_early_init(void)
 	 */
 	pm_write8(0xd2, 0);
 }
-#endif
-- 
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